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PIC18FXX39 Data Sheet
Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel
2002 Microchip Technology Inc.
Preliminary
DS30485A
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS30485A - page ii
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
Enhanced FLASH Microcontrollers with Single Phase Induction Motor Control Kernel
High Performance RISC CPU:
* Linear program memory addressing to 24 Kbytes * Linear data memory addressing to 1.4 Kbytes * 20 MHz operation (5 MIPs): - 20 MHz oscillator/clock input - 5 MHz oscillator/clock input with PLL active * 16-bit wide instructions, 8-bit wide data path * 8 x 8 Single Cycle Hardware Multiplier
Peripheral Features:
* High current sink/source 25 mA/25 mA * Three external interrupt pins * Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler * Timer1 module: 16-bit timer/counter * Timer3 module: 16-bit timer/counter * Secondary oscillator clock option - Timer1/Timer3 * Two PWM modules: - Resolution is 1- to 10-bit, Max. PWM freq. @ 8-bit resolution = 156 kHz 10-bit resolution = 39 kHz * Single Phase Induction Motor Control kernel - Programmable Motor Control Technology (ProMPTTM) provides open loop Variable Frequency (VF) control - User programmable Voltage vs. Frequency curve - Most suitable for shaded pole and permanent split capacitor type motors * Master Synchronous Serial Port (MSSP) module with two modes of operation: - 3-wire SPITM (supports all 4 SPI modes) - I2CTM Master and Slave mode * Addressable USART module: - Supports RS-485 and RS-232 * Parallel Slave Port (PSP) module
Special Microcontroller Features:
* 100,000 erase/write cycle Enhanced FLASH program memory typical * 1,000,000 erase/write cycle Data EEPROM memory * FLASH/Data EEPROM Retention: > 100 years * Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Programmable code protection * Power saving SLEEP mode * Single supply 5V In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * In-Circuit Debug (ICD) via two pins
Analog Features:
* Compatible 10-bit Analog-to-Digital Converter module (A/D) with: - Fast sampling rate - Conversion available during SLEEP - DNL = 1 LSb, INL = 1 LSb * Programmable Low Voltage Detection (PLVD) - Supports interrupt on Low Voltage Detection * Programmable Brown-out Reset (BOR)
CMOS Technology:
* Low power, high speed FLASH/EEPROM technology * Fully static design * Wide operating voltage range (2.0V to 5.5V) * Industrial and Extended temperature ranges
Program Memory Device PIC18F2439 PIC18F2539 PIC18F4439 PIC18F4539 Bytes 12K 24K 12K 24K Words 6144 12288 6144 12288
Data Memory SRAM (Bytes) 640 1408 640 1408
I/O 10-bit EEPROM Pins A/D (ch) (Bytes) 256 256 256 256 21 21 32 32 5 5 8 8
PWM 10-bit 2 2 2 2
MSSP SPI Yes Yes Yes Yes Master I2C Yes Yes Yes Yes AUSART Yes Yes Yes Yes
Timers 16-bit/WDT 3/1 3/1 3/1 3/1
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 1
PIC18FXX39
Pin Diagrams
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL PWM1 PWM2 NC
44-Pin TQFP
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT0 RB1/INT1 RB2/INT2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC18F4439 PIC18F4539
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T13CKI OSC2/CLKO/RA6 OSC1/CLKI VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI
22 21 20 19 18 17 16 15 14 13 12
RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5/PGM RB4 NC NC
44-Pin QFN
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL PWM2 PWM1 RC0/T13CKI RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD AVDD RB0/INT0 RB1/INT1 RB2/INT2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34
PIC18F4439 PIC18F4539
33 32 31 30 29 28 27 26 25 24 23
OSC2/CLKO/RA6 OSC1/CLKI VSS AVSS VDD VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS/LVDIN RA4/T0CKI
22 21 20 19 18 17 16 15 14 13 12 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5/PGM RB4 NC RB3
DS30485A-page 2
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
Pin Diagrams (Cont.'d)
40-Pin DIP
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS VDD VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T13CKI PWM2 PWM1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2/INT2 RB1/INT1 RB0/INT0 VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
PIC18F4439
28-Pin DIP, SOIC
MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T13CKI PWM2 PWM1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/PGD RB6/PGC RB5/PGM RB4 RB3 RB2/INT2 RB1/INT1 RB0/INT0 VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
PIC18F2439
2002 Microchip Technology Inc.
Preliminary
PIC18F2539
PIC18F4539
DS30485A-page 3
PIC18FXX39
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 19 3.0 Reset .......................................................................................................................................................................................... 23 4.0 Memory Organization ................................................................................................................................................................. 33 5.0 FLASH Program Memory ........................................................................................................................................................... 51 6.0 Data EEPROM Memory ............................................................................................................................................................. 61 7.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 67 8.0 Interrupts .................................................................................................................................................................................... 69 9.0 I/O Ports ..................................................................................................................................................................................... 83 10.0 Timer0 Module ........................................................................................................................................................................... 99 11.0 Timer1 Module ......................................................................................................................................................................... 103 12.0 Timer2 Module ......................................................................................................................................................................... 107 13.0 Timer3 Module ......................................................................................................................................................................... 109 14.0 Single Phase Induction Motor Control Kernel .......................................................................................................................... 113 15.0 Pulse Width Modulation (PWM) Modules ................................................................................................................................. 123 16.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 125 17.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 165 18.0 Compatible 10-bit Analog-to-Digital Converter (A/D) Module................................................................................................... 181 19.0 Low Voltage Detect .................................................................................................................................................................. 189 20.0 Special Features of the CPU .................................................................................................................................................... 195 21.0 Instruction Set Summary .......................................................................................................................................................... 211 22.0 Development Support............................................................................................................................................................... 253 23.0 Electrical Characteristics .......................................................................................................................................................... 259 24.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 287 25.0 Packaging Information.............................................................................................................................................................. 297 Appendix A: Revision History............................................................................................................................................................. 305 Appendix B: Device Differences......................................................................................................................................................... 305 Appendix C: Conversion Considerations ........................................................................................................................................... 306 Appendix D: Migration from High-End to Enhanced Devices............................................................................................................. 307 Index .................................................................................................................................................................................................. 309 On-Line Support................................................................................................................................................................................. 317 Systems Information and Upgrade Hot Line ...................................................................................................................................... 317 Reader Response .............................................................................................................................................................................. 318 PIC18FXX39 Product Identification System....................................................................................................................................... 319
DS30485A-page 4
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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2002 Microchip Technology Inc.
Preliminary
DS30485A-page 5
PIC18FXX39
NOTES:
DS30485A-page 6
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
1.0 DEVICE OVERVIEW
1.2
This document contains device specific information for the following devices: * PIC18F2439 * PIC18F2539 * PIC18F4439 * PIC18F4539
Details on Individual Family Members
Devices in the PIC18FXX39 family are available in 28-pin (PIC18F2X39) and 40/44-pin (PIC18F4X39) packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in four ways: 1. FLASH program memory and data RAM (12 Kbytes and 640 bytes for PIC18FX439 devices, 24 Kbytes and 1408 bytes for PIC18FX539) A/D channels (5 for PIC18F2X39 devices, 8 for PIC18F4X39) I/O ports (3 ports on PIC18F2X39, 5 ports on PIC18F4X39 devices) Parallel Slave Port (present only on PIC18F4X39 devices)
This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high-endurance Enhanced FLASH program memory. The PIC18FXX39 family also provides an off-the-shelf solution for simple motor control applications, allowing users to create speed control solutions with small part counts and short development times.
2. 3. 4.
1.1
1.1.1
Key Features
PROGRAMMABLE MOTOR PROCESSOR TECHNOLOGY (ProMPTTM) MOTOR CONTROL
The integrated motor control kernel uses on-chip Pulse Width Modulation (PWM) to provide speed control for single phase induction motors. Through a convenient set of Application Program Interfaces (APIs) and variable frequency technology for open loop control, users can develop applications with little or no previous experience in motor control techniques. ProMPT motor control provides modulated output over a range of 0 to 127 Hz, and has a pre-defined V/F curve that can be reprogrammed to suit the application.
All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3.
1.1.2
OTHER PIC18FXX39 FEATURES
* Memory Endurance: The Enhanced FLASH cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory, and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years at 25C. * Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Addressable USART: This serial communication module is capable of standard RS-232 operation using the internal oscillator block, removing the need for an external crystal (and its accompanying power requirement) in applications that talk to the outside world. * 10-bit A/D Converter: This module offers up to 8 conversion channels for flexibility in sensor monitoring and control, as well as the ability to do conversions while the device is in SLEEP mode.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 7
PIC18FXX39
TABLE 1-1: PIC18FXX39 DEVICE FEATURES
PIC18F2439 DC - 40 MHz 12K 6144 640 256 15 Ports A, B, C 3
(1)
Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources I/O Ports Timers PWM Modules Single Phase Induction Motor Control Serial Communications Parallel Communications 10-bit Analog-to-Digital Module
PIC18F2539 DC - 40 MHz 24K 12288 1408 256 15 Ports A, B, C 3 2 Yes MSSP, Addressable USART -- 5 input channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST) Yes Yes 75 Instructions 28-pin DIP 28-pin SOIC
PIC18F4439 DC - 40 MHz 12K 6144 640 256 16 3 2 Yes MSSP, Addressable USART PSP 8 input channels
PIC18F4539 DC - 40 MHz 24K 12288 1408 256 16 3 2 Yes MSSP, Addressable USART PSP 8 input channels
Ports A, B, C, D, E Ports A, B, C, D, E
2 Yes MSSP, Addressable USART -- 5 input channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST) Yes Yes 75 Instructions 28-pin DIP 28-pin SOIC
RESETS (and Delays)
POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) Yes Yes 75 Instructions 40-pin DIP 44-pin TQFP 44-pin QFN Yes Yes 75 Instructions 40-pin DIP 44-pin TQFP 44-pin QFN
Programmable Low Voltage Detect Programmable Brown-out Reset Instruction Set Packages
Note 1: PWM modules are used exclusively in conjunction with the motor control kernel, and are not available for other applications.
DS30485A-page 8
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 1-1: PIC18F2X39 BLOCK DIAGRAM
Data Bus<8>
21 21
Table Pointer
Data Latch
PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6
8
inc/dec logic
8
8
Data RAM
Address Latch Address Latch
21
PCLATU PCLATH
12
(2)
Program Memory (up to 2 Mbytes)
Data Latch
PCU PCH PCL Program Counter
Address<12>
4
BSR
12
FSR0 FSR1 FSR2 inc/dec logic
4
Bank0, F
31 Level Stack
12 PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3 RB4 RB5/PGM RB6/PGC RB7/PGD 8
16
Table Latch
Decode
8
ROM Latch
Instruction Register
Instruction Decode & Control OSC2/CLKO OSC1/CLKI T1OSCI T1OSCO Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset 4X PLL Precision Voltage Reference Watchdog Timer Brown-out Reset Low Voltage Programming In-Circuit Debugger 3
PRODH PRODL 8 x 8 Multiply
8
BIT OP WREG
PORTC 8 RC0/T13CKI RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
8 8
8
ALU<8>
8
MCLR VDD, VSS
PWM1 PWM2
Timer0
Timer1
Timer2
Timer3
A/D Converter
PWM1
PWM2
Master Synchronous Serial Port
Addressable
USART
Data EEPROM
Note
1: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 2: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 9
PIC18FXX39
FIGURE 1-2: PIC18F4X39 BLOCK DIAGRAM
Data Bus<8> PORTA 21 21
Table Pointer
Data Latch 8 8 8 Data RAM (up to 4K address reach) Address Latch
(2)
inc/dec logic 21
RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6 PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3 RB4 RB5/PGM RB6/PGC RB7/PGD PORTC
Address Latch Program Memory (up to 2 Mbytes) Data Latch
PCLATU PCLATH
PCU PCH PCL Program Counter 31 Level Stack
12 Address<12> 4
BSR
12 FSR0 FSR1 FSR2
inc/dec logic
4
Bank0, F
12
16
Table Latch
Decode
8
ROM Latch
Instruction Register
Instruction Decode & Control OSC2/CLKO OSC1/CLKI T1OSCI T1OSCO Timing Generation Power-up Timer Oscillator Start-up Timer Power-on Reset 4X PLL Precision Voltage Reference Watchdog Timer Brown-out Reset Low Voltage Programming In-Circuit Debugger 3
8 PRODH PRODL 8 x 8 Multiply 8 BIT OP 8 WREG 8 8 ALU<8> PORTE 8 8
RC0/T13CKI RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS
MCLR VDD, VSS
PWM1 PWM2
Timer0
Timer1
Timer2
Timer3
A/D Converter
PWM1
PWM2
Master Synchronous Serial Port
Addressable USART
Parallel Slave Port
Data EEPROM
Note
1: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF instruction). 2: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The multiplexing combinations are device dependent.
DS30485A-page 10
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 1-2:
Pin Name MCLR/VPP MCLR VPP NC OSC1/CLKI OSC1 CLKI -- 9 -- 9 I I CMOS CMOS
PIC18F2X39 PINOUT I/O DESCRIPTIONS
Pin Number DIP 1 Pin Type SOIC 1 I I -- ST ST -- Buffer Type Description Master Clear (input) or high voltage ICSP programming enable pin. Master Clear (Reset) input. This pin is an active low RESET to the device. High voltage ICSP programming enable pin. These pins should be left unconnected. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In EC mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bi-directional I/O port.
OSC2/CLKO/RA6 OSC2 CLKO
10
10 O O -- --
RA6 RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 T0CKI RA5/AN4/SS/LVDIN RA5 AN4 SS LVDIN RA6 Legend: TTL ST O OD = = = = 2 2
I/O
TTL
I/O I 3 3 I/O I 4 4 I/O I I 5 5 I/O I I 6 6 I/O I 7 7 I/O I I I
TTL Analog TTL Analog TTL Analog Analog TTL Analog Analog ST/OD ST TTL Analog ST Analog
Digital I/O. Analog input 0. Digital I/O. Analog input 1. Digital I/O. Analog input 2. A/D Reference Voltage (Low) input. Digital I/O. Analog input 3. A/D Reference Voltage (High) input. Digital I/O. Open drain when configured as output. Timer0 external clock input. Digital I/O. Analog input 4. SPI Slave Select input. Low Voltage Detect input. See the OSC2/CLKO/RA6 pin. CMOS = CMOS compatible input or output I = Input P = Power
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 11
PIC18FXX39
TABLE 1-2:
Pin Name
PIC18F2X39 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number DIP Pin Type SOIC Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/INT0 RB0 INT0 RB1/INT1 RB1 INT1 RB2/INT2 RB2 INT2 RB3 RB4 RB5/PGM RB5 PGM RB6/PGC RB6 PGC RB7/PGD RB7 PGD Legend: TTL ST O OD = = = =
21
21 I/O I TTL ST TTL ST TTL ST TTL TTL Digital I/O. External interrupt 0. Digital I/O. External interrupt 1. Digital I/O. External interrupt 2. Digital I/O. Digital I/O. Interrupt-on-change pin. Digital I/O. Interrupt-on-change pin. Low Voltage ICSP programming enable pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power
22
22 I/O I
23
23 I/O I
24 25 26
24 25 26
I/O I/O
I/O I/O 27 27 I/O I/O 28 28 I/O I/O
TTL ST TTL ST TTL ST
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
DS30485A-page 12
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 1-2:
Pin Name
PIC18F2X39 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number DIP 11 Pin Type SOIC 11 I/O I 14 14 I/O I/O I/O 15 15 I/O I I/O 16 16 I/O O 17 17 I/O O I/O 18 18 I/O I I/O 13 12 8, 19 20 = = = = 13 12 8, 19 20 O O P P ST ST ST -- -- -- -- Digital I/O. USART Asynchronous Receive. USART Synchronous Data (see related TX/CK). PWM Channel 1 (motor control) output. PWM Channel 2 (motor control) output. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. CMOS = CMOS compatible input or output I = Input P = Power ST -- ST Digital I/O. USART Asynchronous Transmit. USART Synchronous Clock (see related RX/DT). ST -- Digital I/O. SPI Data out. ST ST ST Digital I/O. SPI Data in. I2C Data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST ST Digital I/O. Timer1/Timer3 external clock input. Buffer Type Description PORTC is a bi-directional I/O port.
RC0/T13CKI RC0 T13CKI RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT PWM1 PWM2 VSS VDD Legend: TTL ST O OD
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 13
PIC18FXX39
TABLE 1-3:
Pin Name MCLR/VPP MCLR VPP OSC1/CLKI OSC1 CLKI 13 32 30 I I CMOS CMOS
PIC18F4X39 PINOUT I/O DESCRIPTIONS
Pin Number DIP 1 QFN 18 Pin Type TQFP 18 I I ST ST Buffer Type Description Master Clear (input) or high voltage ICSP programming enable pin. Master Clear (Reset) input. This pin is an active low RESET to the device. High voltage ICSP programming enable pin. Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In EC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. PORTA is a bi-directional I/O port.
OSC2/CLKO/RA6 OSC2 CLKO
14
33
31 O O -- --
RA6 RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 T0CKI RA5/AN4/SS/LVDIN RA5 AN4 SS LVDIN RA6 Legend: TTL ST O OD = = = = 2 19 19
I/O
TTL
I/O I 3 20 20 I/O I 4 21 21 I/O I I 5 22 22 I/O I I 6 23 23 I/O I 7 24 24 I/O I I I
TTL Analog TTL Analog TTL Analog Analog TTL Analog Analog ST/OD ST TTL Analog ST Analog
Digital I/O. Analog input 0. Digital I/O. Analog input 1. Digital I/O. Analog input 2. A/D Reference Voltage (Low) input. Digital I/O. Analog input 3. A/D Reference Voltage (High) input. Digital I/O. Open drain when configured as output. Timer0 external clock input. Digital I/O. Analog input 4. SPI Slave Select input. Low Voltage Detect input. (See the OSC2/CLKO/RA6 pin.) CMOS = CMOS compatible input or output I = Input P = Power
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
DS30485A-page 14
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 1-3:
Pin Name
PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number DIP QFN Pin Type TQFP Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.
RB0/INT0 RB0 INT0 RB1/INT1 RB1 INT1 RB2/INT2 RB2 INT2 RB3 RB4 RB5/PGM RB5 PGM RB6/PGC RB6 PGC RB7/PGD RB7 PGD Legend: TTL ST O OD = = = =
33
9
8 I/O I TTL ST TTL ST TTL ST TTL TTL TTL ST TTL ST Digital I/O. External interrupt 0. Digital I/O. External interrupt 1. Digital I/O. External interrupt 2. Digital I/O. Digital I/O. Interrupt-on-change pin. Digital I/O. Interrupt-on-change pin. Low Voltage ICSP programming enable pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power
34
10
9 I/O I
35
11
10 I/O I
36 37 38
12 14 15
11 14 15
I/O I/O I/O I/O
39
16
16 I/O I/O
40
17
17 I/O I/O TTL ST
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 15
PIC18FXX39
TABLE 1-3:
Pin Name
PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number DIP 15 QFN 34 Pin Type TQFP 32 I/O I 18 37 37 I/O I/O I/O 23 42 42 I/O I I/O 24 43 43 I/O O 25 44 44 I/O O I/O 26 1 1 I/O I I/O 17 16 = = = = 35 36 36 35 O O ST ST ST -- -- Digital I/O. USART Asynchronous Receive. USART Synchronous Data (see related TX/CK). PWM Channel 1 (motor control) output. PWM Channel 2 (motor control) output. CMOS = CMOS compatible input or output I = Input P = Power ST -- ST Digital I/O. USART Asynchronous Transmit. USART Synchronous Clock (see related RX/DT). ST -- Digital I/O. SPI Data out. ST ST ST Digital I/O. SPI Data in. I2C Data I/O. ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. ST ST Digital I/O. Timer1/Timer3 external clock input. Buffer Type Description PORTC is a bi-directional I/O port.
RC0/T13CKI RC0 T13CKI RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT PWM1 PWM2 Legend: TTL ST O OD
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
DS30485A-page 16
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 1-3:
Pin Name
PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number DIP QFN Pin Type TQFP Buffer Type Description PORTD is a bi-directional I/O port, or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled.
RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5 RD5 PSP5 RD6/PSP6 RD6 PSP6 RD7/PSP7 RD7 PSP7 Legend: TTL ST O OD = = = =
19
38
38
I/O ST TTL Digital I/O. Parallel Slave Port Data. Digital I/O. Parallel Slave Port Data. Digital I/O. Parallel Slave Port Data. Digital I/O. Parallel Slave Port Data. Digital I/O. Parallel Slave Port Data. Digital I/O. Parallel Slave Port Data. Digital I/O. Parallel Slave Port Data. Digital I/O. Parallel Slave Port Data. CMOS = CMOS compatible input or output I = Input P = Power
20
39
39
I/O ST TTL
21
40
40
I/O ST TTL
22
41
41
I/O ST TTL
27
2
2
I/O ST TTL
28
3
3
I/O ST TTL
29
4
4
I/O ST TTL
30
5
5
I/O ST TTL
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 17
PIC18FXX39
TABLE 1-3:
Pin Name
PIC18F4X39 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number DIP 8 QFN 25 Pin Type TQFP 25 I/O ST TTL Analog 9 26 26 I/O ST TTL Analog 10 27 27 I/O ST TTL Analog 12, 31 6, 31 11, 32 7, 28, 29 -- -- -- = = = = 30 8 13 6, 29 7, 28 -- -- 12, 13, 33, 34 P P P P -- -- -- -- -- -- Digital I/O. Chip Select control for parallel slave port (see related RD and WR). Analog input 7. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. Ground reference for analog modules. Positive supply for analog modules. These pins should be left unconnected. CMOS = CMOS compatible input or output I = Input P = Power Digital I/O. Write control for parallel slave port (see CS and RD pins). Analog input 6. Digital I/O. Read control for parallel slave port (see also WR and CS pins). Analog input 5. Buffer Type Description PORTE is a bi-directional I/O port.
RE0/RD/AN5 RE0 RD AN5 RE1/WR/AN6 RE1 WR AN6 RE2/CS/AN7 RE2 CS AN7 VSS VDD AVSS AVDD NC Legend: TTL ST O OD
TTL compatible input Schmitt Trigger input with CMOS levels Output Open Drain (no P diode to VDD)
DS30485A-page 18
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
2.0
2.1
OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 2-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS CONFIGURATION)
OSC1 To Internal Logic SLEEP
C1(1)
The PIC18FXX39 can be operated in four different Oscillator modes at a frequency of 20 MHz. The user can program three configuration bits (FOSC2, FOSC1, and FOSC0) to select one of these four modes: 1. 2. HS HS + PLL High Speed Crystal/Resonator High Speed Crystal/Resonator with PLL enabled using 5 MHz crystal External Clock External Clock with I/O pin enabled
C2(1)
XTAL
RS(2) OSC2
RF(3)
PIC18FXX39
3. 4.
EC ECIO Note:
Note 1: See Table 2-1 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the Oscillator mode chosen.
The operation of the Motor Control kernel and its APIs (Section 14.0) is based on an assumed clock frequency of 20 MHz. Changing the oscillator frequency will change the timing used in the Motor Control kernel accordingly. To achieve the best results in motor control applications, a clock frequency of 20 MHz is highly recommended.
An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2.
FIGURE 2-2:
EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)
OSC1
2.2
Crystal Oscillator/Ceramic Resonators
Clock from Ext. System Open
PIC18FXX39
OSC2
In HS or HS+PLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The PIC18FXX39 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications.
Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components, or verify oscillator performance.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 19
PIC18FXX39
TABLE 2-1: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Ranges Tested: Mode HS Freq 20.0 MHz C1 15-33 pF C2 15-33 pF
Clock from Ext. System FOSC/4
FIGURE 2-3:
EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)
OSC1
PIC18FXX39
OSC2
These values are for design guidance only. See notes following this table. Crystals Used 20.0 MHz Epson CA-301 20.000M-C 30 PPM
Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: Rs may be required in HS mode to avoid overdriving crystals with low drive level specification. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components, or verify oscillator performance.
The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-4 shows the pin connections for the ECIO Oscillator mode.
FIGURE 2-4:
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1
Clock from Ext. System RA6
PIC18FXX39
I/O (OSC2)
2.4 2.3 External Clock Input
The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC Oscillator mode.
HS/PLL
A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 5 MHz, the internal clock frequency will be multiplied to 20 MHz. This is useful for customers who are concerned with EMI due to high frequency crystals. The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. If they are programmed for any other mode, the PLL is not enabled and the system clock will come directly from OSC1. The PLL is one of the modes specified by the FOSC<2:0> configuration bits. The Oscillator mode is specified during device programming. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out that is called TPLL.
DS30485A-page 20
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 2-5: PLL BLOCK DIAGRAM
HS Osc (from Configuration bit Register) PLL Enable
OSC2
Phase Comparator FIN Crystal Osc FOUT Loop Filter VCO MUX SYSCLK
OSC1
/4
2.5
Effects of SLEEP Mode on the On-Chip Oscillator
When the device executes a SLEEP instruction, the oscillator is turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during SLEEP will increase the current consumed during SLEEP. The user can wake from SLEEP through external RESET, Watchdog Timer Reset, or through an interrupt.
The first timer is the Power-up Timer (PWRT), which optionally provides a fixed delay of 72 ms (nominal) on power-up only (POR and BOR). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. With the PLL enabled (HS/PLL Oscillator mode), the time-out sequence following a Power-on Reset is different from other Oscillator modes. The time-out sequence is as follows: 1. 2. The PWRT time-out is invoked after a POR time delay has expired. The Oscillator Start-up Timer (OST) is invoked. However, this is still not a sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional fixed 2 ms (nominal) time-out to allow the PLL ample time to lock to the incoming clock frequency.
2.6
Power-up Delays
3.
Power-up delays are controlled by two timers, so that no external RESET circuitry is required for most applications. The delays ensure that the device is kept in RESET, until the device power supply and clock are stable. For additional information on RESET operation, see Section 3.0.
TABLE 2-2:
OSC Mode ECIO EC HS Note:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin Floating Floating Feedback inverter disabled, at quiescent voltage level OSC2 Pin Configured as PORTA, bit 6 At logic low Feedback inverter disabled, at quiescent voltage level
See Table 3-1 in the "Reset" section, for time-outs due to SLEEP and MCLR Reset.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 21
PIC18FXX39
NOTES:
DS30485A-page 22
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
3.0 RESET
The PIC18FXX39 differentiates between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different RESET situations, as indicated in Table 3-2. These bits are used in software to determine the nature of the RESET. See Table 3-3 for a full description of the RESET states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. The MCLR pin is not driven low by any internal RESETS, including the WDT.
Most registers are unaffected by a RESET. Their status is unknown on POR and unchanged by all other RESETS. The other registers are forced to a "RESET state" on Power-on Reset, MCLR, WDT Reset, Brownout Reset, MCLR Reset during SLEEP and by the RESET instruction.
FIGURE 3-1:
RESET Instruction Stack Pointer
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset External Reset
MCLR WDT Module VDD Rise Detect VDD Brown-out Reset OST/PWRT
SLEEP WDT Time-out Reset Power-on Reset S
BOREN
OST 10-bit Ripple Counter OSC1 PWRT 10-bit Ripple Counter R Q
Chip_Reset
On-chip RC OSC(1)
Enable PWRT Enable OST(2)
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin. 2: See Table 3-1 for time-out situations.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 23
PIC18FXX39
3.1 Power-on Reset (POR) 3.3 Oscillator Start-up Timer (OST)
A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (i.e., exits the RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 32). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.
3.4
PLL Lock Time-out
FIGURE 3-2:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
With the PLL enabled, the time-out sequence following a Power-on Reset is different from other Oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the Oscillator Start-up Time-out (OST).
3.5
Brown-out Reset (BOR)
D
R R1 C MCLR
PIC18FXXXX
Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
A configuration bit, BOREN, can disable (if clear/ programmed), or enable (if set) the Brown-out Reset circuitry. If VDD falls below parameter D005 for greater than parameter 35, the brown-out situation will reset the chip. A RESET may not occur if VDD falls below parameter D005 for less than parameter 35. The chip will remain in Brown-out Reset until VDD rises above BVDD. If the Power-up Timer is enabled, it will be invoked after VDD rises above BVDD; it then will keep the chip in RESET for an additional time delay (parameter 33). If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute the additional time delay.
3.6
Time-out Sequence
3.2
Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out (parameter 33) only on power-up from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip-to-chip due to VDD, temperature and process variation. See DC parameter D033 for details.
On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after the POR time delay has expired. Then, OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18FXXX device operating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all the registers.
DS30485A-page 24
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) PWRTE = 0 72 ms + 1024 TOSC + 2ms 72 ms + 1024 TOSC 72 ms 72 ms PWRTE = 1 1024 TOSC + 2 ms 1024 TOSC -- -- Brown-out 72 ms(2) + 1024 TOSC + 2 ms 72 ms(2) + 1024 TOSC 72 ms
(2)
Oscillator Configuration HS with PLL enabled(1) HS, XT, LP EC External RC
Wake-up from SLEEP or Oscillator Switch 1024 TOSC + 2 ms 1024 TOSC -- --
72 ms(2)
Note 1: 2 ms is the nominal time required for the 4x PLL to lock. 2: 72 ms is the nominal power-up timer delay, if implemented.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0 IPEN bit 7 Note 1: Refer to Section 4.14 (page 50) for bit definitions. U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER
Program Counter 0000h 0000h 0000h 0000h 0000h 0000h 0000h PC + 2 0000h PC + 2(1) RCON Register 0--1 1100 0--u uuuu 0--0 uuuu 0--u uu11 0--u uu11 0--u 10uu 0--u 01uu u--u 00uu 0--1 11u0 u--u 00uu RI 1 u 0 u u u 1 u 1 u TO 1 u u u u 1 0 0 1 1 PD 1 u u u u 0 1 0 1 0 POR 0 u u u u u u u 1 u BOR 0 u u u u u u u 0 u STKFUL u u u u 1 u u u u u STKUNF u u u 1 u u u u u u
Condition Power-on Reset MCLR Reset during normal operation Software Reset during normal operation Stack Full Reset during normal operation Stack Underflow Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h).
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 25
PIC18FXX39
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices Power-on Reset, Brown-out Reset ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A MCLR Resets WDT Reset RESET Instruction Stack Resets ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 -1-1 11-0 0-00 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A Wake-up via WDT or Interrupt ---0 uuuu(1) uuuu uuuu(1) uuuu uuuu(1) uu-u uuuu(1) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(3) uuuu -u-u(3) uu-u u-uu(3) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A
TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1
2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. * These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.
DS30485A-page 26
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset ---- xxxx xxxx xxxx ---- 0000 N/A N/A N/A N/A N/A ---- xxxx xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 ---- ---0 --00 0101 ---- ---0 0--q 11qq xxxx xxxx xxxx xxxx 0-00 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets ---- uuuu uuuu uuuu ---- 0000 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu 1111 1111 ---- ---0 --00 0101 ---- ---0 0--q qquu uuuu uuuu uuuu uuuu u-uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 Wake-up via WDT or Interrupt ---- uuuu uuuu uuuu ---- uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- ---u --uu uuuu ---- ---u u--u qquu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu 1111 1111 -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON
(4) *
2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539
*
TMR1H TMR1L T1CON TMR2 PR2* T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2
*
2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. * These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.
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PIC18FXX39
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset xxxx xxxx xxxx xxxx 0000 00-0 00-- 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 -010 0000 000x 0000 0000 0000 0000 xx-0 x000 ---- ---MCLR Resets WDT Reset RESET Instruction Stack Resets uuuu uuuu uuuu uuuu 0000 00-0 00-- 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 -010 0000 000x 0000 0000 0000 0000 uu-0 u000 ---- ---Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uu-u uu-- uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uu-0 u000 ---- ----
ADRESH ADRESL ADCON0 ADCON1 CCPR1H CCPR1L* CCP1CON CCPR2H CCPR2L TMR3H TMR3L T3CON SPBRG RCREG TXREG TXSTA RCSTA EEADR EEDATA EECON1 EECON2
* *
2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539
CCP2CON*
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. * These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.
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TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices Power-on Reset, Brown-out Reset ---1 1111 ---0 0000 ---0 0000 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 0000 -111 1111 1111 1111 1111 1111 1111 -111 1111(5) ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx(5) ---- -000 xxxx xxxx xxxx xxxx xxxx xxxx -x0x 0000(5) MCLR Resets WDT Reset RESET Instruction Stack Resets ---1 1111 ---0 0000 ---0 0000 1111 1111 -111 1111 0000 0000 -000 0000 0000 0000 -000 0000 0000 -111 1111 1111 1111 1111 1111 1111 -111 1111(5) ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu(5) ---- -000 uuuu uuuu uuuu uuuu uuuu uuuu -u0u 0000(5) Wake-up via WDT or Interrupt ---u uuuu ---u uuuu(3) ---u uuuu uuuu uuuu -uuu uuuu uuuu uuuu(3) -uuu uuuu(3) uuuu uuuu -uuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu(5) ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu(5) ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu(5)
IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 TRISE TRISD TRISC* TRISB TRISA(5,6) LATE LATD LATC* LATB LATA
(5,6)
2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539 2439 4439 2539 4539
PORTE PORTD PORTC* PORTB PORTA
(5,6)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. * These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits are reserved. Users should not modify the value of these bits. See Section 4.9.2 for details. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other Oscillator modes, they are disabled and read `0'. 6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.
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Preliminary
DS30485A-page 29
PIC18FXX39
FIGURE 3-3:
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TOST
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
FIGURE 3-4:
VDD MCLR INTERNAL POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
TPWRT TOST
PWRT TIME-OUT OST TIME-OUT INTERNAL RESET
FIGURE 3-5:
VDD MCLR INTERNAL POR
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET
TOST
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PIC18FXX39
FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V
FIGURE 3-7:
TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD)
VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL
PLL TIME-OUT INTERNAL RESET
Note:
TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer.
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PIC18FXX39
NOTES:
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PIC18FXX39
4.0 MEMORY ORGANIZATION
There are three memory blocks in Enhanced MCU devices. These memory blocks are: * Program Memory * Data RAM * Data EEPROM Data and program memory use separate busses, which allows for concurrent access of these blocks. Additional detailed information for FLASH program memory and Data EEPROM is provided in Section 5.0 and Section 6.0, respectively. The PIC18F2539 and PIC18F4539 each have a total of 24 Kbytes, or 12K of single word instructions of FLASH memory, from addresses 0000h to 5FFFh. The next 8 Kbytes beyond this space (from 6000h to 7FFFh) are reserved for the Motor Control kernel; accessing locations in this range will return random information. The PIC18F2439 and PIC18F4439 each have 12 Kbytes, or 6K of single word instructions of FLASH memory, from addresses 0000h to 2FFFh. The next 4 Kbytes of this space (from 3000h to 3FFFh) are reserved for the Motor Control kernel; accessing locations in this range will return random information. The RESET vector address for all devices is at 0000h, and the interrupt vector addresses are at 0008h and 0018h. The memory maps for the PIC18FX439 PIC18FX539 devices are shown in Figure 4-1. Note: and
4.1
Program Memory Organization
A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the top of the 2-MByte range will cause a read of all `0's (a NOP instruction).
The ProMPT Motor Control kernel is identical for all PIC18FXX39 devices, regardless of the difference in reserved block size between PIC18FX439 and PIC18FX539 devices
FIGURE 4-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18FXX39 DEVICES
PC<20:0> CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1
* * *
21
Stack Level 31 PIC18FX439 Devices RESET Vector 0000h PIC18FX539 Devices RESET Vector 0000h
High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory 2FFFh 3000h 3FFFh 4000h
High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h
On-Chip Program Memory User Memory Space
Reserved
5FFFh 6000h Reserved Read '0' 7FFFh 8000h
Read '0' 1FFFFFh 200000h Note: Size of memory areas not to scale. 1FFFFFh 200000h
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Preliminary
DS30485A-page 33
PIC18FXX39
4.2 Return Address Stack
4.2.2
The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all RESETS. There is no RAM associated with stack pointer 00000b. This is only a RESET value. During a CALL type instruction, causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC. During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the stack pointer is decremented. The stack space is not part of either program or data space. The stack pointer is readable and writable, and the address on the top of the stack is readable and writable through SFR registers. Data can also be pushed to, or popped from the stack using the top-of-stack SFRs. Status bits indicate if the stack pointer is at, or beyond the 31 levels provided.
RETURN STACK POINTER (STKPTR)
The STKPTR register contains the stack pointer value, the STKFUL (stack full) status bit, and the STKUNF (stack underflow) status bits. Register 4-1 shows the STKPTR register. The value of the stack pointer can be 0 through 31. The stack pointer increments when values are pushed onto the stack and decrements when values are popped off the stack. At RESET, the stack pointer value will be `0'. The user may read and write the stack pointer value. This feature can be used by a Real-Time Operating System for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit can only be cleared in software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. Refer to Section 21.0 for a description of the device configuration bits. If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit, and reset the device. The STKFUL bit will remain set and the stack pointer will be set to `0'. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. Any additional pushes will not overwrite the 31st push, and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the stack pointer remains at `0'. The STKUNF bit will remain set until cleared in software or a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the RESET vector, where the stack conditions can be verified and appropriate actions can be taken.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL hold the contents of the stack location pointed to by the STKPTR register. This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user must disable the global interrupt enable bits during this time to prevent inadvertent stack operations.
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PIC18FXX39
REGISTER 4-1: STKPTR REGISTER
R/C-0 STKFUL bit 7 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as '0' SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/C-0 STKUNF U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0
bit 6(1)
bit 5 bit 4-0
FIGURE 4-2:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack 11111 11110 11101 TOSU 0x00 TOSH 0x1A TOSL 0x34 00011 Top-of-Stack 0x001A34 00010 0x000D58 00001 00000
STKPTR<4:0> 00010
4.2.3
PUSH AND POP INSTRUCTIONS
4.2.4
STACK FULL/UNDERFLOW RESETS
Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place a return address on the stack. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value.
These RESETS are enabled by programming the STVREN configuration bit. When the STVREN bit is disabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device RESET. When the STVREN bit is enabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit and then cause a device RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR Reset.
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Preliminary
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PIC18FXX39
4.3 Fast Register Stack
For PIC18FXX39 devices, a "fast interrupt return" option is available for high priority interrupts. A single level Fast Register Stack is provided for the STATUS, WREG and BSR registers; it is not readable or writable. When the processor vectors for an interrupt, the stack is loaded with the current value of the corresponding register. If the FAST RETURN instruction is used to return from the interrupt, the values in the registers are then loaded back into the working registers. Note: The fast interrupt return for PIC18FXX39 devices is reserved for use by the ProMPT kernel and the Timer2 match interrupt. It is not available to the user for any other interrupts or returns from subroutines. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 4.8.1).
4.4
PCL, PCLATH and PCLATU
4.5
Clocking Scheme/Instruction Cycle
The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register.
The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-3.
FIGURE 4-3:
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode)
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Internal Phase Clock PC Execute INST (PC-2) Fetch INST (PC) PC+2 PC+4
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+2) Fetch INST (PC+4)
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4.6 Instruction Flow/Pipelining
An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 4-1). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
EXAMPLE 4-1:
INSTRUCTION PIPELINE FLOW
TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h 2. MOVWF PORTB 3. BRA 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
4.7
Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 4-4 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read `0' (see Section 4.4).
The CALL and GOTO instructions have an absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 4-4 shows how the instruction, `GOTO 000006h', is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single word instructions that the PC will be offset by. Section 21.0 provides further details of the instruction set.
FIGURE 4-4:
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h
Program Memory Byte Locations
Instruction 1: Instruction 2: Instruction 3:
MOVLW GOTO MOVFF
055h 000006h 123h, 456h
0Fh EFh F0h C1h F4h
55h 03h 00h 23h 56h
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PIC18FXX39
4.7.1 TWO-WORD INSTRUCTIONS
The PIC18FXX39 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to `1's and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that changes the PC. A program example that demonstrates this concept is shown in Example 4-2. Refer to Section 21.0 for further details of the instruction set.
EXAMPLE 4-2:
CASE 1: Object Code
TWO-WORD INSTRUCTIONS
Source Code TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; 2nd operand holds address of REG2 REG3 ; continue code REG1, REG2 ; No, execute 2-word instruction
0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000
Source Code TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; 2nd operand becomes NOP REG3 ; continue code REG1, REG2 ; Yes
4.8
Lookup Tables
4.8.2
TABLE READS/TABLE WRITES
Lookup tables are implemented two ways. These are: * Computed GOTO * Table Reads
A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. Lookup table data may be stored 2 bytes per program word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time. A description of the Table Read/Table Write operation is shown in Section 5.1.
4.8.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, that returns the value 0xnn to the calling function. The offset value (value in WREG) specifies the number of bytes that the program counter should advance. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Note: The ADDWF PCL instruction does not update PCLATH and PCLATU. A read operation on PCL must be performed to update PCLATH and PCLATU.
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4.9 Data Memory Organization
4.9.1
The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The data memory map is divided into 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user's application. The SFRs start at the last location of Bank 15 (FFFh) and extend downwards. Any remaining space beyond the SFRs in the Bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as `0's. The organization of the data memory space for these devices is shown in Figure 4-5 and Figure 4-6. PIC18FX439 devices have 640 bytes of data RAM, extending from Bank 0 to Bank 2 (000h through 27Fh). The block of 128 bytes above this to the top of the bank (280h to 2FFh) is used as data memory for the Motor Control kernel, and is not available to the user. Reading these locations will return random information that reflects the kernel's "scratch" data. Modifying the data in these locations may disrupt the operation of the ProMPT kernel. PIC18FX539 devices have 1408 bytes of data RAM, extending from Bank 0 to Bank 5 (000h through 57Fh). As with the PIC18FX439 devices, the block of 128 bytes above this to the end of the bank (580h to 5FFh) is used by the Motor Control kernel. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without banking. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing, or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 provides a detailed description of the Access RAM.
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indirectly. Indirect addressing operates using a File Select Register and corresponding Indirect File Operand. The operation of indirect addressing is shown in Section 4.12. Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other RESETS. Data RAM is available for use as GPR registers by all instructions. The top half of Bank 15 (F80h to FFFh) contains SFRs. All other banks of data memory contain GPR registers, starting with Bank 0.
4.9.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 4-1 and Table 4-2. The SFRs can be classified into two sets; those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as '0's. See Table 4-1 for addresses for the SFRs. Note: In this chapter and throughout this document, certain SFR names and individual bits are marked with an asterisk (*). This denotes registers that are not implemented in PIC18FXX39 devices, but whose names are retained to maintain compatibility with PIC18FXX2 devices. The designated bits within these registers are reserved and may be used by certain modules or the Motor Control kernel. Users should not write to these registers or alter these bit values. Failure to do this may result in erratic microcontroller operation.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 39
PIC18FXX39
FIGURE 4-5:
BSR<3:0> = 0000 = 0001 = 0010 = 0011
00h
DATA MEMORY MAP FOR PIC18FX439
Data Memory Map
Access RAM GPR GPR FFh 00h GPR ProMPT Memory 1FFh 200h 27Fh 280h 2FFh 300h 000h 07Fh 080h 0FFh 100h
Bank 0
FFh 00h
Bank 1 Bank 2
FFh
Access Bank
*
*
Bank 3 to Bank 14
Unused Read `00h'
7Fh Access RAM High 80h (SFRs) FFh
Access RAM Low
00h
*
= 1110 = 1111
00h Unused SFR EFFh F00h F7Fh F80h FFFh
When a = 0, the BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15).
Bank 15
FFh
When a = 1, the BSR is used to specify the RAM location that the instruction uses.
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PIC18FXX39
FIGURE 4-6:
BSR<3:0> = 0000
00h
DATA MEMORY MAP FOR PIC18FX539
Data Memory Map
Access RAM GPR GPR FFh 00h FFh 00h 1FFh 200h GPR 2FFh 300h GPR FFh 3FFh 400h GPR 00h GPR ProMPT Memory 4FFh 500h 5FFh 600h 000h 07Fh 080h 0FFh 100h
Bank 0
FFh 00h
= 0001
Bank 1 Bank 2
= 0010
= 0011
Bank 3
= 0100
Bank 4
Access Bank 7Fh Access RAM High 80h (SFRs) FFh Access RAM Low 00h
= 0101
Bank 5
FFh
= 0110
*
*
*
Bank 6 to Bank 14
Unused Read `00h'
= 1110
00h EFFh F00h F7Fh F80h FFFh
When a = 0, the BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15).
= 1111
Bank 15
FFh
Unused SFR
When a = 1, the BSR is used to specify the RAM location that the instruction uses.
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Preliminary
DS30485A-page 41
PIC18FXX39
TABLE 4-1:
Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h
SPECIAL FUNCTION REGISTER MAP
Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(3) POSTINC0(3) Address FDFh FDEh FDDh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h Name INDF2(3) POSTINC2(3) POSTDEC2(3) PREINC2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON -- OSCCON* LVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2* PR2* T2CON* SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 --
(3)
Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h
Name CCPR1H CCPR1L
*
Address F9Fh F9Eh F9Dh F9Ch F9Bh
*
Name IPR1 PIR1 PIE1 -- -- -- -- -- -- TRISE(2) TRISD(2) TRISC(4) TRISB TRISA -- -- -- -- LATE(2) LATD(2) LATC(4) LATB LATA -- -- -- -- PORTE(2) PORTD(2) PORTC(4) PORTB PORTA
CCP1CON* CCPR2H CCPR2L* CCP2CON -- -- -- -- -- -- TMR3H TMR3L T3CON -- SPBRG RCREG TXREG TXSTA RCSTA -- EEADR EEDATA EECON2 EECON1 -- -- -- IPR2 PIR2 PIE2
PLUSW2(3)
F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h
POSTDEC0(3) PREINC0(3) PLUSW0(3) FSR0H FSR0L WREG INDF1(3) POSTINC1(3) POSTDEC1(3) PREINC1(3) PLUSW1(3) FSR1H FSR1L BSR
* These registers are retained to maintain compatibility with PIC18FXX2 devices; however, one or more bits are reserved in PIC18FXX39 devices. Users should not alter the values of these bits. Note 1: Unimplemented registers are read as `0'. 2: This register is not available on PIC18F2X39 devices. 3: This is not a physical register. 4: Bits 1 and 2 are reserved; users should not alter their values.
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PIC18FXX39
TABLE 4-2:
File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS Legend: * Note 1: 2: 3:
REGISTER FILE SUMMARY
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: ---0 0000 0000 0000 0000 0000 Return Stack Pointer Holding Register for PC<20:16> 00-0 0000 ---0 0000 0000 0000 0000 0000 bit21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 -- INT0IE INTEDG2 INT2IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 1111 -1-1 11-0 0-00 n/a n/a n/a n/a n/a 26, 34 26, 34 26, 34 26, 35 26, 36 26, 36 26, 36 26, 54 26, 54 26, 54 26, 54 26, 67 26, 67 26, 71 26, 72 26, 73 26, 47 26, 47 26, 47 26, 47 26, 47 26, 47 26, 47 26 26, 47 26, 47 26, 47 26, 47 26, 47 27, 47 27, 47 27, 46 27, 47 27, 47 27, 47 27, 47 27, 47 27, 47 27, 47 27, 49
Top-of-Stack Upper Byte (TOS<20:16>)
Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL -- STKUNF -- -- --
Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 (not a physical register). Offset by value in WREG. -- Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 (not a physical register). Offset by value in WREG. -- -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 1 Low Byte Bank Select Register Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 (not a physical register). Offset by value in WREG. -- -- -- -- -- -- -- N Indirect Data Memory Address Pointer 2 Low Byte OV Z DC C -- -- -- Indirect Data Memory Address Pointer 0 Low Byte
Indirect Data Memory Address Pointer 0 High Byte ---- 0000 xxxx xxxx xxxx xxxx n/a n/a n/a n/a n/a
Indirect Data Memory Address Pointer 1 High Byte ---- 0000 xxxx xxxx ---- 0000 n/a n/a n/a n/a n/a
Indirect Data Memory Address Pointer 2 High Byte ---- 0000 xxxx xxxx ---x xxxx
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details. RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. Bit 21 of the TBLPTRU allows access to the device configuration bits. These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.
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Preliminary
DS30485A-page 43
PIC18FXX39
TABLE 4-2:
File Name TMR0H TMR0L T0CON OSCCON* LVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2* PR2* T2CON* SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 CCPR1H CCPR1L* CCP1CON* CCPR2H CCPR2L* CCP2CON* TMR3H TMR3L T3CON SPBRG RCREG TXREG TXSTA RCSTA EEADR EEDATA EECON2 EECON1 Legend: * Note 1: 2: 3:
REGISTER FILE SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Details POR, BOR on page: 0000 0000 xxxx xxxx T0CS -- IRVST -- -- T0SE -- LVDEN -- RI PSA -- LVDL3 -- TO T0PS2 -- LVDL2 -- PD T0PS1 -- LVDL1 -- POR T0PS0 * LVDL0 SWDTE BOR 1111 1111 ---- ---0 --00 0101 ---- ---0 27, 101 27, 101 27, 99 27 27, 191 27, 203 27, 103 27, 103 27, 103 27 27 27 27, 125 27, 134 27, 126 27, 127 27, 137
Timer0 Register High Byte Timer0 Register Low Byte TMR0ON -- -- -- IPEN T08BIT -- -- -- --
0--1 11qq 25, 50, 80 xxxx xxxx xxxx xxxx
Timer1 Register High Byte Timer1 Register Low Byte RD16 * * * -- * * * T1CKPS1 * * * T1CKPS0 * * * -- * * * T1SYNC * * * TMR1CS * * * * * *
TMR1ON 0-00 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000
SSP Receive Buffer/Transmit Register SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode. SMP WCOL GCEN CKE SSPOV ACKSTAT D/A SSPEN ACKDT P CKP ACKEN S SSPM3 RCEN R/W SSPM2 PEN UA SSPM1 RSEN BF SSPM0 SEN
A/D Result Register High Byte A/D Result Register Low Byte ADCS1 ADFM * -- * -- ADCS0 ADCS2 * -- * -- CHS2 -- * * * * CHS1 -- * * * * CHS0 PCFG3 * * * * GO/DONE PCFG2 * * * * -- PCFG1 * * * * ADON PCFG0 * * * *
xxxx xxxx 187,188 xxxx xxxx 187,188 0000 00-0 00-- 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx 28, 181 28, 182 28, 124 28, 124 28, 124 28, 124 28, 124 28, 124 28, 109 28, 109 28, 109 28, 168
PWM Register1 High Byte (Read only)
PWM Register2 High Byte (Read only)
Timer3 Register High Byte Timer3 Register Low Byte RD16 -- T3CKPS1 T3CKPS0 -- T3SYNC TMR3CS USART1 Baud Rate Generator USART1 Receive Register USART1 Transmit Register CSRC SPEN TX9 RX9 TXEN SREN SYNC CREN -- ADDEN BRGH FERR TRMT OERR TX9D RX9D
TMR3ON 0000 0000 0000 0000
0000 0000 28, 175, 178 0000 0000 28, 173, 176 0000 -010 0000 000x 0000 0000 0000 0000 ---- ---WREN WR RD xx-0 x000 28, 166 28, 167 28, 61, 65 28, 65 28, 61, 65 28, 62
Data EEPROM Address Register Data EEPROM Data Register Data EEPROM Control Register 2 (not a physical register) EEPGD CFGS -- FREE WRERR
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details. RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. Bit 21 of the TBLPTRU allows access to the device configuration bits. These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 4-2:
File Name IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 TRISE(3) TRISD(3) TRISC TRISB TRISA LATE(3) LATD(3) LATC LATB LATA PORTE(3) PORTD PORTC PORTB PORTA Legend: * Note 1: 2: 3:
(3)
REGISTER FILE SUMMARY (CONTINUED)
Bit 7 -- -- -- PSPIP(3) PSPIF(3) PSPIE(3) IBF TRISC7 -- -- Bit 6 -- -- -- ADIP ADIF ADIE OBF TRISC6 Bit 5 -- -- -- RCIP RCIF RCIE IBOV TRISC5 Bit 4 EEIP EEIF EEIE TXIP TXIF TXIE PSPMODE TRISC4 Bit 3 BCLIP BCLIF BCLIE SSPIP SSPIF SSPIE -- TRISC3 Bit 2 LVDIP LVDIF LVDIE -- -- -- Bit 1 TMR3IP TMR3IF TMR3IE TMR2IP TMR2IF TMR2IE Bit 0 -- -- -- TMR1IP TMR1IF TMR1IE Value on Details POR, BOR on page: ---1 1111 ---0 0000 ---0 0000 1111 1111 0000 0000 0000 0000 0000 -111 1111 1111 * * TRISC0 1111 1111 1111 1111 -111 1111 ---- -xxx xxxx xxxx LATC3 * Latch(1) * LATC0 xxxx xxxx xxxx xxxx -xxx xxxx ---- -000 xxxx xxxx RC3 * * RC0 xxxx xxxx xxxx xxxx -x0x 0000 29, 79 29, 75 29, 77 29, 78 29, 74 29, 76 29, 94 29, 92 29, 89 29, 86 29, 83 29, 95 29, 91 29, 89 29, 86 29, 83 29, 95 29, 91 29, 89 29, 86 29, 83
Data Direction bits for PORTE
Data Direction Control Register for PORTD Data Direction Control Register for PORTB TRISA6(1) Data Direction Control Register for PORTA -- -- -- -- Read PORTE Data Latch, Write PORTE Data Latch
Read PORTD Data Latch, Write PORTD Data Latch LATC7 -- LATC6 LATA6(1) LATC5 LATC4 Read PORTB Data Latch, Write PORTB Data Latch Read PORTA Data Latch, Write PORTA Data
Read PORTE pins, Write PORTE Data Latch Read PORTD pins, Write PORTD Data Latch RC7 -- RC6 RA6(1) RC5 RC4 Read PORTB pins, Write PORTB Data Latch Read PORTA pins, Write PORTA Data Latch(1)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition These registers (or individual bits) are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in PIC18FXX39 devices. Users should not alter the values of these bits. See Section 4.9.2 for details. RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator modes. Bit 21 of the TBLPTRU allows access to the device configuration bits. These registers and bits are reserved on the PIC18F2X39 devices; always maintain these clear.
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Preliminary
DS30485A-page 45
PIC18FXX39
4.10 Access Bank 4.11 Bank Select Register (BSR)
The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: * * * * * Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read `0's, and writes will have no effect. A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all `0's and all writes are ignored. The STATUS register bits will be set/cleared as appropriate for the instruction performed. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 4.12 provides a description of indirect addressing, which allows linear addressing of the entire RAM space.
The Access Bank is comprised of the upper 128 bytes in Bank 15 (SFRs) and the lower 128 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 4-5 and Figure 4-6 indicate the Access RAM areas. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register, or in the Access Bank. This bit is denoted by the `a' bit (for access bit). When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function registers, so that these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits.
FIGURE 4-7:
DIRECT ADDRESSING
Direct Addressing
BSR<3:0> 7 From Opcode(3) 0
Bank Select(2)
Location Select(3) 00h 000h 01h 100h 0Eh E00h 0Fh F00h
Data Memory(1)
0FFh
1FFh
EFFh
FFFh
Bank 0
Note 1: For register file map detail, see Table 4-1.
Bank 1
Bank 14
Bank 15
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
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Preliminary
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PIC18FXX39
4.12 Indirect Addressing, INDF and FSR Registers
the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all '0's are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the STATUS bits are not affected.
Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-8 shows the operation of indirect addressing. This shows the moving of the value to the data memory address specified by the value of the FSR register. Indirect addressing is possible by using one of the INDF registers. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF register indirectly, results in a NOP operation. The FSR register contains a 12-bit address, which is shown in Figure 4-9. The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 4-3 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions.
4.12.1
INDIRECT ADDRESSING OPERATION
Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation on one of these five registers determines how the FSR will be modified during indirect addressing. When data access is done to one of the five INDFn locations, the address selected will configure the FSRn register to: * Do nothing to FSRn after an indirect access (no change) - INDFn * Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn * Auto-increment FSRn after an indirect access (post-increment) - POSTINCn * Auto-increment FSRn before an indirect access (pre-increment) - PREINCn * Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect address causes the FSR to equal '0', the Z bit will not be set. Incrementing or decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a stack pointer, in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSR to form the address, before an indirect access. The FSR value is not changed. If an FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (STATUS bits are not affected). If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions.
EXAMPLE 4-3:
HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING
FSR0 ,0x100 ; POSTINC0 ; Clear INDF ; register and ; inc pointer BTFSS FSR0H, 1 ; All done with ; Bank1? GOTO NEXT ; NO, clear next CONTINUE ; YES, continue NEXT
LFSR CLRF
There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bits wide. To store the 12 bits of addressing information, two 8-bit registers are required. These indirect addressing registers are: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L
In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads
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Preliminary
DS30485A-page 47
PIC18FXX39
FIGURE 4-8: INDIRECT ADDRESSING OPERATION
RAM Instruction Executed Opcode Address FFFh 12 File Address = Access of an Indirect Addressing Register 0h
BSR<3:0> Instruction Fetched Opcode 4
12 8 File
12
FSR
FIGURE 4-9:
INDIRECT ADDRESSING
Indirect Addressing
11 FSR Register 0
Location Select
0000h
Data Memory(1)
0FFFh Note 1: For register file map detail, see Table 4-1.
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2002 Microchip Technology Inc.
PIC18FXX39
4.13 STATUS Register
The STATUS register, shown in Register 4-2, contains the arithmetic status of the ALU. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV, or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV, or N bits from the STATUS register. For other instructions not affecting any status bits, see Table 21-2. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction.
REGISTER 4-2:
STATUS REGISTER
U-0 -- bit 7 U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC R/W-x C bit 0
bit 7-5 bit 4
Unimplemented: Read as '0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register.
bit 3
bit 2
bit 1
bit 0
C: Carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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4.14 RCON Register
The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device RESET. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. For PIC18FXX39 devices, the IPEN bit must always be set (= 1) for the ProMPT kernel to function correctly. Refer to Section 8.0 (page 69) for a more detailed discussion. Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is `1' on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will be cleared, and must be set by firmware to indicate the occurrence of the next Brown-out Reset. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected.
REGISTER 4-3:
RCON REGISTER
R/W-0 IPEN bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
bit 7 bit 6-5 bit 4
IPEN: Interrupt Priority Enable bit Always maintain this bit set for proper operation of ProMPT kernel. Unimplemented: Read as '0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device RESET (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3
bit 2
bit 1
bit 0
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5.0 FLASH PROGRAM MEMORY
5.1 Table Reads and Table Writes
The FLASH Program Memory is readable, writable, and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16-bits wide, while the data RAM space is 8-bits wide. Table Reads and Table Writes move data between these two memory spaces through an 8-bit register (TABLAT). Table Read operations retrieve data from program memory and places it into the data RAM space. Figure 5-1 shows the operation of a Table Read with program memory and data RAM. Table Write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 5.5, "Writing to FLASH Program Memory". Figure 5-2 shows the operation of a Table Write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a Table Write is being used to write executable code into program memory, program instructions will need to be word aligned.
FIGURE 5-1:
TABLE READ OPERATION
Instruction: TBLRD*
Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL
Program Memory Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer points to a byte in program memory.
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FIGURE 5-2: TABLE WRITE OPERATION
Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 5.5.
5.2
Control Registers
Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers
The FREE bit, when set, will allow a program memory erase operation. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset, during normal operation. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), due to RESET values of zero. Control bit WR initiates write operations. This bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software.
5.2.1
EECON1 AND EECON2 REGISTERS
EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit EEPGD determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on configuration registers, regardless of EEPGD (see Section 20.0, "Special Features of the CPU"). When clear, memory selection access is determined by EEPGD.
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REGISTER 5-1: EECON1 REGISTER (ADDRESS FA6h)
R/W-x EEPGD bit 7 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access FLASH program memory 0 = Access data EEPROM memory CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access FLASH program or data EEPROM memory Unimplemented: Read as '0' FREE: FLASH Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only WRERR: FLASH Program/Data EE Error Flag bit 1 = A write operation is prematurely terminated (any RESET during self-timed programming in normal operation) 0 = The write operation completed Note: bit 2 When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6
bit 5 bit 4
bit 3
WREN: FLASH Program/Data EE Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 1
bit 0
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5.2.2 TABLAT - TABLE LATCH REGISTER 5.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes, and erases of the FLASH program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer, TBLPTR (TBLPTR<21:3>), will determine which program memory block of 8 bytes is written to. For more detail, see Section 5.5 ("Writing to FLASH Program Memory"). When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 5-3 describes the relevant boundaries of TBLPTR based on FLASH program memory operations.
5.2.3
TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the Device ID, the User ID and the Configuration bits. The table pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 5-1. These operations on the TBLPTR only affect the low order 21 bits.
TABLE 5-1:
Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write
FIGURE 5-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
ERASE - TBLPTR<21:6> WRITE - TBLPTR<21:3> READ - TBLPTR<21:0>
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5.3 Reading the FLASH Program Memory
TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 5-4 shows the interface between the internal program memory and the TABLAT.
The TBLRD instruction is used to retrieve data from program memory and place into data RAM. Table Reads from program memory are performed one byte at a time.
FIGURE 5-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register (IR)
FETCH
TBLRD
TABLAT Read Register
EXAMPLE 5-1:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD
READING A FLASH PROGRAM MEMORY WORD
CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word
TBLRD*+ MOVF TABLAT, W MOVWF WORD_EVEN TBLRD*+ MOVF TABLAT, W MOVWF WORD_ODD
; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data
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5.4 Erasing FLASH Program memory
5.4.1
The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control can larger blocks of program memory be bulk erased. Word erase in the FLASH array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased; TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the FLASH program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal FLASH. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal program memory location is: 1. 2. Load table pointer with address of row being erased. Set EEPGD bit to point to program memory, clear CFGS bit to access program memory, set WREN bit to enable writes, and set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Re-enable interrupts.
3. 4. 5. 6. 7. 8.
EXAMPLE 5-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1,EEPGD EECON1,CFGS EECON1,WREN EECON1,FREE INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE ; load TBLPTR with the base ; address of the memory block
ERASE_ROW BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF ; ; ; ; ; point to FLASH program memory access FLASH program memory enable write to memory enable Row Erase operation disable interrupts
Required Sequence
; write 55h ; write AAh ; start erase (CPU stall) ; re-enable interrupts
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5.5 Writing to FLASH Program Memory
operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal FLASH. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations.
The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table Writes are used internally to load the holding registers needed to program the FLASH memory. There are 8 holding registers used by the Table Writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the Table Write
FIGURE 5-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT Write Register
8
TBLPTR = xxxxx0 TBLPTR = xxxxx1
8
TBLPTR = xxxxx2
8
TBLPTR = xxxxx7
8
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
5.5.1
FLASH PROGRAM MEMORY WRITE SEQUENCE
The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure. Load Table Pointer with address of first byte being written. Write the first 8 bytes into the holding registers with auto-increment (TBLWT*+ or TBLWT+*). Set EEPGD bit to point to program memory, clear the CFGS bit to access program memory, and set WREN to enable byte writes. Disable interrupts. Write 55h to EECON2.
10. Write AAh to EECON2. 11. Set the WR bit. This will begin the write cycle. 12. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Repeat steps 6-14 seven times, to write 64 bytes. 15. Verify the memory (Table Read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 5-3. Note: Before setting the WR bit, the table pointer address needs to be within the intended address range of the 8 bytes in the holding registers.
8. 9.
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EXAMPLE 5-3:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_BLOCK TBLRD*+ MOVF MOVWF DECFSZ BRA MODIFY_WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BSF EECON1,EEPGD BCF EECON1,CFGS BSF EECON1,WREN BSF EECON1,FREE BCF INTCON,GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1,WR BSF INTCON,GIE TBLRD*WRITE_BUFFER_BACK MOVLW 8 MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 MOVWF COUNTER WRITE_WORD_TO_HREGS MOVF POSTINC0, W MOVWF TABLAT TBLWT+* DECFSZ COUNTER BRA WRITE_WORD_TO_HREGS ; load TBLPTR with the base ; address of the memory block DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer TABLAT, W POSTINC0 COUNTER READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat
WRITING TO FLASH PROGRAM MEMORY
D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block ; point to buffer
; Load TBLPTR with the base ; address of the memory block
; update buffer word
; ; ; ; ;
point to FLASH program memory access FLASH program memory enable write to memory enable Row Erase operation disable interrupts
; write 55h ; ; ; ; write AAh start erase (CPU stall) re-enable interrupts dummy read decrement
; number of write buffer groups of 8 bytes ; point to buffer
; number of bytes in holding register
; ; ; ; ;
get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full
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EXAMPLE 5-3:
PROGRAM_MEMORY BSF BCF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF BSF DECFSZ BRA BCF
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
EECON1,EEPGD EECON1,CFGS EECON1,WREN INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR INTCON,GIE COUNTER_HI PROGRAM_LOOP EECON1,WREN ; ; ; ; point to FLASH program memory access FLASH program memory enable write to memory disable interrupts
; write 55h ; ; ; ; write AAh start program (CPU stall) re-enable interrupts loop until done
; disable write to memory
5.5.2
WRITE VERIFY
5.5.4
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
PROTECTION AGAINST SPURIOUS WRITES
To protect against spurious writes to FLASH program memory, the write initiate sequence must also be followed. See "Special Features of the CPU" (Section 20.0) for more detail.
5.5.3
UNEXPECTED TERMINATION OF WRITE OPERATION
5.6
FLASH Program Operation During Code Protection
If a write is terminated by an unplanned event, such as loss of power or an unexpected RESET, the memory location just programmed should be verified and reprogrammed if needed.The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location.
See "Special Features of the CPU" (Section 20.0) for details on code protection of FLASH program memory.
TABLE 5-2:
Name TBLPTRU Bit 7 --
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 6 -- Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on All Other RESETS
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) TABLAT INTCON EECON2 EECON1 IPR2 PIR2 PIE2 Legend: Program Memory Table Latch GIE/GIEH PEIE/GIEL EEPGD -- -- -- CFGS -- -- -- TMR0IE -- -- -- -- INTE FREE EEIP EEIF EEIE RBIE WRERR BCLIP BCLIF BCLIE TMR0IF WREN LVDIP LVDIF LVDIE INTF WR TMR3IP TMR3IF TMR3IE RBIF RD -- -- -- EEPROM Control Register2 (not a physical register)
0000 000x 0000 000u -- --
xx-0 x000 uu-0 u000 ---1 1111 ---1 1111 ---0 0000 ---0 0000 ---0 0000 ---0 0000
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used during FLASH/EEPROM access.
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NOTES:
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6.0 DATA EEPROM MEMORY
6.1 EEADR
The Data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: * * * * EECON1 EECON2 EEDATA EEADR The address register can address up to a maximum of 256 bytes of data EEPROM.
6.2
EECON1 and EECON2 Registers
EECON1 is the control register for EEPROM memory accesses. EECON2 is not a physical register. Reading EECON2 will read all '0's. The EECON2 register is used exclusively in the EEPROM write sequence. Control bits RD and WR initiate read and write operations, respectively. These bits cannot be cleared, only set, in software. They are cleared in hardware at the completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental or premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), due to the RESET condition forcing the contents of the registers to zero. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software.
The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 0h to FFh. The EEPROM data memory is rated for high erase/ write cycles. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip to chip. Please refer to parameter D122 (Electrical Characteristics, Section 23.0) for exact limits.
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REGISTER 6-1: EECON1 REGISTER (ADDRESS FA6h)
R/W-x EEPGD bit 7 bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit 1 = Access FLASH program memory 0 = Access data EEPROM memory CFGS: FLASH Program/Data EE or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access FLASH program or data EEPROM memory Unimplemented: Read as '0' FREE: FLASH Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only WRERR: FLASH Program/Data EE Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-timed programming in normal operation) 0 = The write operation completed Note: bit 2 When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6
bit 5 bit 4
bit 3
WREN: FLASH Program/Data EE Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 1
bit 0
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6.3 Reading the Data EEPROM Memory
(EECON1<6>), and then set control bit RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>), clear the CFGS control bit
EXAMPLE 6-1:
MOVLW MOVWF BCF BCF BSF MOVF
DATA EEPROM READ
DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, CFGS EECON1, RD EEDATA, W ; ; ; ; ; ; Data Memory Address to read Point to DATA memory Access program FLASH or Data EEPROM memory EEPROM Read W = EEDATA
6.4
Writing to the Data EEPROM Memory
To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. Then, the sequence in Example 6-2 must be followed to initiate the write cycle. The write will not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, EECON1, EEADR and EDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Write Complete Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt, or poll this bit. EEIF must be cleared by software.
EXAMPLE 6-2:
DATA EEPROM WRITE
MOVLW MOVWF MOVLW MOVWF BCF BCF BSF DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, CFGS EECON1, WREN ; ; ; ; ; ; ; Data Memory Address to read Data Memory Value to write Point to DATA memory Access program FLASH or Data EEPROM memory Enable writes
Required Sequence
BCF MOVLW MOVWF MOVLW MOVWF BSF BSF
INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR INTCON, GIE
; ; ; ; ; ; ;
Disable interrupts Write 55h Write AAh Set WR bit to begin write Enable interrupts
. . . BCF
; user code execution
EECON1, WREN
; Disable writes on write complete (EEIF set)
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6.5 Write Verify 6.7 Operation During Code Protect
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Data EEPROM memory has its own code protect mechanism. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal Data EEPROM, regardless of the state of the code protect configuration bit. Refer to "Special Features of the CPU" (Section 20.0) for additional information.
6.6
Protection Against Spurious Write
There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction.
6.8
Using the Data EEPROM
The data EEPROM is a high endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in FLASH program memory. A simple data EEPROM refresh routine is shown in Example 6-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124.
EXAMPLE 6-3:
clrf bcf bcf bcf bsf Loop bsf movlw movwf movlw movwf bsf btfsc bra incfsz bra bcf bsf
DATA EEPROM REFRESH ROUTINE
EEADR EECON1,CFGS EECON1,EEPGD INTCON,GIE EECON1,WREN EECON1,RD 55h EECON2 AAh EECON2 EECON1,WR EECON1,WR $-2 EEADR,F Loop EECON1,WREN INTCON,GIE ; ; ; ; ; ; ; ; ; ; ; ; ; Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write AAh Set WR bit to begin write Wait for write to complete
; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts
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TABLE 6-1:
Address FF2h FA9h FA8h FA7h FA6h FA2h FA1h FA0h Legend:
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Bit 7 GIE/ GIEH Bit 6 PEIE/ GIEL Bit 5 T0IE Bit 4 INTE Bit 3 RBIE Bit 2 T0IF Bit 1 INTF Bit 0 RBIF Value on: POR, BOR 0000 000x 0000 0000 0000 0000 -- WR TMR3IP TMR3IF TMR3IE RD -- -- -- xx-0 x000 ---1 1111 ---0 0000 ---0 0000 FREE EEIP EEIF EEIE WRERR BCLIP BCLIF BCLIE WREN LVDIP LVDIF LVDIE Value on All Other RESETS 0000 000u 0000 0000 0000 0000 -- uu-0 u000 ---1 1111 ---0 0000 ---0 0000
Name INTCON EEADR EEDATA EECON1 IPR2 PIR2 PIE2
EEPROM Address Register EEPROM Data Register EEPGD -- -- -- CFGS -- -- -- -- -- -- --
EECON2 EEPROM Control Register2 (not a physical register)
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used during FLASH/EEPROM access.
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NOTES:
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7.0
7.1
8 X 8 HARDWARE MULTIPLIER
Introduction
7.2
Operation
An 8 x 8 hardware multiplier is included in the ALU of the PIC18FXX39 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the ALUSTA register. Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: * Higher computational throughput * Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Table 7-1 shows a performance comparison between enhanced devices using the single cycle hardware multiply, and performing the same function without the hardware multiply.
Example 7-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 7-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done.
EXAMPLE 7-1:
MOVF MULWF ARG1, W ARG2
8 x 8 UNSIGNED MULTIPLY ROUTINE
; ; ARG1 * ARG2 -> ; PRODH:PRODL
EXAMPLE 7-2:
MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, ARG2 W
8 x 8 SIGNED MULTIPLY ROUTINE
; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1
ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F
; Test Sign Bit ; PRODH = PRODH ; - ARG2
TABLE 7-1:
Routine
PERFORMANCE COMPARISON
Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.8 s 25.4 s 4.0 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16.0 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s
8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed
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Example 7-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 7-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0.
EQUATION 7-2:
16 x 16 SIGNED MULTIPLICATION ALGORITHM
EQUATION 7-1:
16 x 16 UNSIGNED MULTIPLICATION ALGORITHM
ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L)
RES3:RES0
= =
RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) + (-1 * ARG1H<7> * ARG2H:ARG2L * 216)
EXAMPLE 7-4:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE :
16 x 16 SIGNED MULTIPLY ROUTINE
EXAMPLE 7-3:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC
16 x 16 UNSIGNED MULTIPLY ROUTINE
ARG1L, W ARG2L
ARG1L, W ARG2L
; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; ARG1H, W ARG2H
; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ;
ARG1H, W ARG2H
; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; ARG1L, W ARG2H PRODL, RES1, PRODH, RES2, WREG RES3, W F W F F
; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ;
ARG1L, W ARG2H PRODL, RES1, PRODH, RES2, WREG RES3, W F W F F
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
ARG1H, W ARG2L PRODL, RES1, PRODH, RES2, WREG RES3, W F W F F
ARG1H * ARG2L -> PRODH:PRODL Add cross products
ARG1H, W ARG2L PRODL, RES1, PRODH, RES2, WREG RES3, W F W F F
ARG1H * ARG2L -> PRODH:PRODL Add cross products
Example 7-4 shows the sequence to do a 16 x 16 signed multiply. Equation 7-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs Most Significant bit (MSb) is tested and the appropriate subtractions are done.
ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3
; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ;
ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3
; ARG1H:ARG1L neg? ; no, done ; ; ;
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8.0 INTERRUPTS
The PIC18FXX39 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2 PIE1, PIE2 IPR1, IPR2 While PIC18FXX39 devices have two interrupt priority levels like other PIC18 microcontrollers, their allocation is different. In these devices, the high priority interrupt is used exclusively by the ProMPT kernel via the Timer2 match interrupt. In order for the kernel to function properly, it is imperative that all other interrupts either set as low priority (IPR bit = 0), or disabled. Note: Disabling interrupts, or setting interrupts as low priority, is not the same as disabling interrupt priorities. The interrupt priority levels must remain enabled (IPEN = 1). Clearing the IPEN bit will result in erratic operation of the ProMPT kernel.
When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIEH or GIEL bits (as applicable), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the Interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source, except INT0, has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits.
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FIGURE 8-1: INTERRUPT LOGIC
Wake-up if in SLEEP mode
TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP
Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR2IF TMR2IE TMR2IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation
Interrupt to CPU Vector to location 0008h
GIEH/GIE
Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP Additional Peripheral Interrupts INT2IF INT2IE INT2IP Interrupt to CPU Vector to Location 0018h
TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP
GIEL/PEIE GIE/GIEH
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8.1 INTCON Registers
Note: The INTCON Registers are readable and writable registers, which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
REGISTER 8-1:
INTCON REGISTER
R/W-0 GIE/GIEH bit 7 R/W-0 PEIE/GIEL R/W-0 TMR0IE R/W-0 INT0IE(1) R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF(2) bit 0
bit 7
GIE/GIEH: Global Interrupt Enable bit 1 = Enables all high priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE(1): INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF(2): RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note 1: Maintain this bit cleared (= 0). 2: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 8-2: INTCON2 REGISTER
R/W-1 RBPU bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge Unimplemented: Read as '0' TMR0IP(1): TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as '0' RBIP(1): RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: Maintain this bit cleared (= 0). Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 INTEDG0 R/W-1 INTEDG1 R/W-1 INTEDG2 U-0 -- R/W-1 TMR0IP U-0 -- R/W-1 RBIP(1) bit 0
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1 bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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REGISTER 8-3: INTCON3 REGISTER
R/W-1 INT2IP(1) bit 7 bit 7 INT2IP(1): INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP(1): INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as '0' INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt Unimplemented: Read as '0' INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Note Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown 1: Maintain this bit cleared (= 0). R/W-1 INT1IP(1) U-0 -- R/W-0 INT2IE R/W-0 INT1IE U-0 -- R/W-0 INT2IF R/W-0 INT1IF bit 0
bit 6
bit 5 bit 4
bit 3
bit 2 bit 1
bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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8.2 PIR Registers
The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag registers (PIR1, PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt.
REGISTER 8-4:
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0 PSPIF(1) bit 7 R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF U-0 -- R/W-0 TMR2IF
(2)
R/W-0 TMR1IF bit 0
bit 7
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit (see Section 17.0 for details on TXIF functionality) 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive Unimplemented: Read as `0' TMR2IF(2): TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = MR1 register did not overflow Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear. 2: This bit is reserved for use by the ProMPT kernel; do not alter its value. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2 bit 1
bit 0
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REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0 -- bit 7 bit 7-5 bit 4 Unimplemented: Read as '0' EEIF: Data EEPROM/FLASH Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete, or has not been started BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred LVDIF: Low Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low Voltage Detect trip point TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 EEIF R/W-0 BCLIF R/W-0 LVDIF R/W-0 TMR3IF U-0 -- bit 0
bit 3
bit 2
bit 1
bit 0
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8.3 PIE Registers
The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
REGISTER 8-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 PSPIE bit 7
(1)
R/W-0 ADIE
R/W-0 RCIE
R/W-0 TXIE
R/W-0 SSPIE
U-0 --
R/W-0 TMR2IE
(2)
R/W-0 TMR1IE bit 0
bit 7
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt Unimplemented: Read as `0' TMR2IE(2): TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2X39 devices; always maintain this bit clear. 2: This bit is reserved for use by the ProMPT kernel; do not alter its value. Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2 bit 1
bit 0
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REGISTER 8-7: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 -- bit 7 bit 7-5 bit 4 Unimplemented: Read as '0' EEIE: Data EEPROM/FLASH Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt Unimplemented: Read as `0' Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-0 EEIE R/W-0 BCLIE R/W-0 LVDIE R/W-0 TMR3IE U-0 -- bit 0
bit 3
bit 2
bit 1
bit 0
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PIC18FXX39
8.4 IPR Registers
In practical terms, this means: * Interrupt priority levels are enabled (IPEN = 1); * High priority interrupts are enabled (INTCON<7> = 1); * Timer2 interrupt is enabled and set as high priority (PIE1<1> and IPR<1> = 1); and * all other interrupts are disabled (INTCON or PIR bits = 0), or set as low priority (IPR bits = 0). Note: Configuring the interrupts is automatically done by the API method void ProMPT_Init(PWMfrequency). It is the user's responsibility to make certain that this method is called at the very beginning of the application. The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1, IPR2). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. For PIC18FXX39 devices, the Motor Control kernel requires that the Timer2 to PR2 match interrupt be the only high priority interrupt. Failure to do this may result in unpredictable operation of the kernel or the entire microcontroller.
REGISTER 8-8:
IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
R/W-1 PSPIP(1,2) bit 7 R/W-1 ADIP(2) R/W-1 RCIP(2) R/W-1 TXIP(2) R/W-1 SSPIP(2) U-1 -- R/W-1 R/W-1 bit 0 TMR2IP(3) TMR1IP(2)
bit 7
PSPIP(1,2): Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority ADIP(2): A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP(2): USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP(2): USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority SSPIP(2): Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `1' TMR2IP(3): TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP(2): TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: This bit is reserved on PIC18F2X39 devices. 2: Maintain this bit cleared (= 0). 3: This bit is reserved for use by the ProMPT kernel; always maintain this bit set (= 1). Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2 bit 1
bit 0
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
REGISTER 8-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
U-0 -- bit 7 bit 7-5 bit 4 Unimplemented: Read as '0' EEIP(1): Data EEPROM/FLASH Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority BCLIP(1): Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority LVDIP(1): Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP(1): TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `1' Note 1: Maintain this bit cleared (= 0). Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-1 EEIP(1) R/W-1 BCLIP(1) R/W-1 LVDIP(1) R/W-1 TMR3IP(1) U-1 -- bit 0
bit 3
bit 2
bit 1
bit 0
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 79
PIC18FXX39
8.5 RCON Register
The RCON register contains the bit which is used to enable prioritized interrupts (IPEN). For PIC18FXX39 devices, the IPEN bit must always be set (= 1) for the ProMPT kernel to function correctly. Refer to page 69 for a more detailed discussion on interrupt priorities.
REGISTER 8-10:
RCON REGISTER
R/W-0 IPEN(1) bit 7 U-0 -- U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0
bit 7
IPEN(1): Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (not used) Unimplemented: Read as '0' RI: RESET Instruction Flag bit For details of bit operation, see Register 4-3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 4-3 PD: Power-down Detection Flag bit For details of bit operation, see Register 4-3 POR: Power-on Reset Status bit For details of bit operation, see Register 4-3 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-3 Note 1: Maintain this bit set (= 1). Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
8.6 INT0 Interrupt 8.7 TMR0 Interrupt
External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxE. Flag bit INTxF must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from SLEEP, if bit INTxE was set prior to going into SLEEP. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. The INT0 interrupt is always configured as a high priority interrupt, and cannot be reconfigured. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). Because it is always configured as a high priority interrupt, INT0 cannot be used in conjunction with the ProMPT kernel; it must always be disabled (INTCON<4> = 0). Failure to do this may result in erratic operation of the motor control. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set flag bit TMR0IF. The interrupt can be enabled or disabled by setting or clearing enable bit TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2<2>). See Section 10.0 for further details on the Timer0 module.
8.8
PORTB Interrupt-on-Change
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled or disabled by setting or clearing the enable bit RBIE (INTCON<3>). Interrupt priority for PORTB interrupton-change is determined by the value contained in the interrupt priority bit RBIP (INTCON2<0>).
8.9
Context Saving During Interrupts
During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 4.3), the user may need to save the WREG, STATUS and BSR registers in software. Depending on the user's application, other registers may also need to be saved. Example 8-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine.
EXAMPLE 8-1:
MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR located anywhere
W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP,STATUS
; Restore BSR ; Restore WREG ; Restore STATUS
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Preliminary
DS30485A-page 81
PIC18FXX39
NOTES:
DS30485A-page 82
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
9.0 I/O PORTS
EXAMPLE 9-1:
CLRF PORTA ; ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTA
Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs
Depending on the device selected, there are either three or five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (data direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch) The data latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving.
CLRF LATA
MOVLW 0x07 MOVWF ADCON1 MOVLW 0xCF
MOVWF TRISA
FIGURE 9-1:
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
9.1
PORTA, TRISA and LATA Registers
RD LATA Data Bus WR LATA or PORTA
PORTA is a 7-bit wide, bi-directional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register reads and writes the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/ T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. The other PORTA pins are multiplexed with analog inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, RA5 and RA3:RA0 are configured as analog inputs and read as `0'. RA6 and RA4 are configured as digital inputs.
D
Q VDD
CK
Q
P N I/O pin(1)
Data Latch D WR TRISA Q
CK
Q
TRIS Latch
VSS Analog Input Mode
RD TRISA Q D
TTL Input Buffer
EN RD PORTA SS Input (RA5 only) To A/D Converter and LVD Modules
Note 1:
I/O pins have protection diodes to VDD and VSS.
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 83
PIC18FXX39
FIGURE 9-2: BLOCK DIAGRAM OF RA4/T0CKI PIN FIGURE 9-3:
ECRA6 or RCRA6 Enable Data Bus RD LATA D CK Q Q N VSS Schmitt Trigger Input Buffer I/O pin(1)
BLOCK DIAGRAM OF RA6 PIN
Data Bus WR LATA or PORTA
RD LATA
Data Latch D WR TRISA CK Q Q
WR LATA or PORTA
D CK
Q Q
VDD P
Data Latch D WR TRISA CK Q Q N I/O pin(1)
TRIS Latch RD TRISA
VSS
TRIS Latch
Q
D RD TRISA EN EN ECRA6 or RCRA6 Enable
TTL Input Buffer
RD PORTA
Q TMR0 Clock Input RD PORTA Note 1: I/O pin has protection diode to VSS only. Note 1:
D EN
I/O pins have protection diodes to VDD and VSS.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 9-1:
Name RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/SS/AN4/LVDIN OSC2/CLKO/RA6
PORTA FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer TTL TTL TTL TTL ST TTL TTL Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF-. Input/output or analog input or VREF+. Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port or analog input, or low voltage detect input. OSC2 or clock output or I/O pin. Function
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 9-2:
Name PORTA LATA TRISA ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 -- -- -- ADFM Bit 6 RA6 Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR -x0x 0000 -xxx xxxx -111 1111 PCFG3 PCFG2 PCFG1 PCFG0 00-- 0000 Value on All Other RESETS -u0u 0000 -uuu uuuu -111 1111 00-- 0000
LATA Data Output Register PORTA Data Direction Register ADCS2 -- --
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 85
PIC18FXX39
9.2 PORTB, TRISB and LATB Registers
The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.
PORTB is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register reads and writes the latched output value for PORTB.
FIGURE 9-4:
RBPU(2) Data Bus WR LATB or PORTB
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q Q I/O pin(1)
EXAMPLE 9-2:
CLRF PORTB ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTB
Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
WR TRISB
CK
TTL Input Buffer
CLRF
LATB
ST Buffer
RD TRISB
MOVLW 0xCF
RD LATB Q RD PORTB EN Set RBIF Q1 Latch D
MOVWF TRISB
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, these pins are configured as digital inputs.
Q From other RB7:RB4 pins RB7:RB5 in Serial Programming mode Note 1: 2:
D EN
RD PORTB Q3
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
Four of the PORTB pins, RB7:RB4, have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'ed together to generate the RB Port Change Interrupt with flag bit, RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. Clear flag bit RBIF.
Note 1: While in Low Voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O pin, and should be held low during normal operation to protect against inadvertent ICSP mode entry. 2: When using Low Voltage ICSP programming (LVP), the pull-up on RB5 becomes disabled. If TRISB bit 5 is cleared, thereby setting RB5 as an output, LATB bit 5 must also be cleared for proper operation.
b)
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 9-5: BLOCK DIAGRAM OF RB2:RB0 PINS
VDD RBPU(2) Data Latch D Q CK TRIS Latch D Q WR TRIS CK TTL Input Buffer I/O pin(1) Weak P Pull-up
Data Bus WR Port
RD TRIS Q RD Port D EN
RB0/INT Schmitt Trigger Buffer
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 9-6:
BLOCK DIAGRAM OF RB3 PIN
VDD RBPU(2) `1' Weak P Pull-up
Data Bus WR LATB or WR PORTB
Data Latch D CK Q
VDD P
TRIS Latch D WR TRISB CK Q
I/O pin(1) N VSS TTL Input Buffer
RD TRISB RD LATB Q D EN RD PORTB
Note 1: 2:
I/O pin has diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 87
PIC18FXX39
TABLE 9-3:
Name RB0/INT0 RB1/INT1 RB2/INT2 RB3 RB4 RB5/PGM(4)
PORTB FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 Buffer TTL/ST
(1)
Function Input/output pin or external interrupt input0. Internal software programmable weak pull-up. Input/output pin or external interrupt input1. Internal software programmable weak pull-up. Input/output pin or external interrupt input2. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Low voltage ICSP enable pin. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data.
TTL/ST(1) TTL/ST(1) TTL TTL TTL/ST(2)
RB6/PGC
bit6
TTL/ST(2)
RB7/PGD
bit7
TTL/ST(2)
Legend: Note 1: 2: 3: 4:
TTL = TTL input, ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on. Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and 40-pin mid-range devices.
TABLE 9-4:
Name PORTB LATB TRISB INTCON INTCON2 INTCON3
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 INT0IE RBIE -- INT1IE TMR0IF TMR0IP -- INT0IF -- INT2IF RBIF RBIP INT1IF 0000 000x 1111 -1-1 11-0 0-00 Value on All Other RESETS uuuu uuuu uuuu uuuu 1111 1111 0000 000u 1111 -1-1 11-0 0-00
LATB Data Output Register PORTB Data Direction Register GIE/ GIEH RBPU INT2IP PEIE/ GIEL INT1IP TMR0IE
INTEDG0 INTEDG1 INTEDG2 -- INT2IE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
9.3 PORTC, TRISC and LATC Registers
EXAMPLE 9-3:
CLRF PORTC ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTC
Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3>,RC<0> as inputs, RC<5:4> as outputs, and RC<7:6> as inputs
PORTC is a 6-bit wide, bi-directional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register reads and writes the latched output value for PORTC. PORTC is multiplexed with the serial communication functions (Table 9-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: On a Power-on Reset, these pins are configured as digital inputs.
CLRF
LATC
MOVLW 0xC9
MOVWF TRISC
PIC18FXX39 devices differ from other PIC18 microcontrollers in allocation of PORTC pins. For most PIC18 devices, PORTC is an 8-bit-wide port. For the PIC18FXX39 family, two of the PORTC pins (RC1 and RC2) are re-allocated as PWM output only pins for use with the Motor Control kernel. To maintain pinout compatibility with other PICmicro(R) devices, the remaining PORTC pins are assigned in a manner consistent with other PIC18 devices. For this reason, PORTC has pins RC0 and RC3 through RC7, but not RC1 and RC2. To maintain compatibility with PIC18FXX2 devices, the individual port and corresponding latch and direction bits for RC1 and RC2 are present in the appropriate registers, but are not available to the user. To avoid erratic device operation, the values of these bits should not be modified.
The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides.
FIGURE 9-7:
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2) Peripheral Data Out VDD
RD LATC Data Bus WR LATC or WR PORTC Data Latch D CK Q Q
1 0
P I/O pin(1)
TRIS Latch D Q WR TRISC CK Q N Schmitt Trigger
RD TRISC Peripheral Output Enable(3) Q D EN
VSS
RD PORTC Peripheral Data In Note 1: 2: 3: I/O pins have diode protection to VDD and VSS.
Port/Peripheral Select signal selects between port data (input) and peripheral output. Peripheral Output Enable is only active if Peripheral Select is active.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 89
PIC18FXX39
TABLE 9-5:
Name RC0/T13CKI RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
PORTC FUNCTIONS
Bit# bit0 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin, Addressable USART Asynchronous Transmit, or Addressable USART Synchronous Clock. Input/output port pin, Addressable USART Asynchronous Receive, or Addressable USART Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 9-6:
Name PORTC LATC TRISC
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 LATC7 TRISC7 Bit 6 RC6 LATC6 TRISC6 Bit 5 RC5 LATC5 TRISC5 Bit 4 RC4 LATC4 TRISC4 Bit 3 RC3 LATC3 TRISC3 Bit 2 * * * Bit 1 * * * Bit 0 RC0 LATC0 TRISC0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on All Other RESETS uuuu uuuu uuuu uuuu 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTC. * Reserved bits; do not modify.
DS30485A-page 90
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
9.4 PORTD, TRISD and LATD Registers
FIGURE 9-8: PORTD BLOCK DIAGRAM IN I/O PORT MODE
This section is applicable only to the PIC18F4X39 devices. PORTD is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register reads and writes the latched output value for PORTD. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs.
RD LATD Data Bus WR LATD or PORTD
D CK
Q I/O pin(1)
Data Latch D WR TRISD CK TRIS Latch RD TRISD Q Schmitt Trigger Input Buffer
Q
D EN EN
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 9.6 for additional information on the Parallel Slave Port (PSP).
RD PORTD
Note 1:
I/O pins have diode protection to VDD and VSS.
EXAMPLE 9-4:
CLRF PORTD ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTD
Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs
CLRF
LATD
MOVLW 0xCF
MOVWF TRISD
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 91
PIC18FXX39
TABLE 9-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
PORTD FUNCTIONS
Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL ST/TTL
(1) (1)
Function Input/output port pin or parallel slave port bit0. Input/output port pin or parallel slave port bit1. Input/output port pin or parallel slave port bit2. Input/output port pin or parallel slave port bit3. Input/output port pin or parallel slave port bit4. Input/output port pin or parallel slave port bit5. Input/output port pin or parallel slave port bit6. Input/output port pin or parallel slave port bit7.
ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL ST/TTL
(1)
ST/TTL(1)
(1)
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 9-8:
Name PORTD LATD TRISD TRISE Bit 7 RD7
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 PSPMODE -- PORTE Data Direction bits 0000 -111 Value on All Other RESETS uuuu uuuu uuuu uuuu 1111 1111 0000 -111
LATD Data Output Register PORTD Data Direction Register IBF OBF IBOV
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.
DS30485A-page 92
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
9.5 PORTE, TRISE and LATE Registers
FIGURE 9-9: PORTE BLOCK DIAGRAM IN I/O PORT MODE
This section is only applicable to the PIC18F4X39 devices. PORTE is a 3-bit wide, bi-directional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register reads and writes the latched output value for PORTE. PORTE has three pins (RE0/AN5/RD, RE1/AN6/WR and RE2/AN7/CS) which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. Register 9-1 shows the TRISE register, which also controls the parallel slave port operation. PORTE pins are multiplexed with analog inputs. When selected as an analog input, these pins will read as '0's. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are configured as analog inputs.
RD LATE Data Bus WR LATE or PORTE
D CK
Q I/O pin(1)
Data Latch D WR TRISE CK TRIS Latch RD TRISE Q Schmitt Trigger Input Buffer
Q
D EN EN
RD PORTE To Analog Converter
Note 1:
I/O pins have diode protection to VDD and VSS.
EXAMPLE 9-5:
CLRF PORTE ; ; ; ; ; ; ; ; ; ; ; ; ; ;
INITIALIZING PORTE
Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RE<0> as inputs RE<1> as outputs RE<2> as inputs
CLRF
LATE
MOVLW MOVWF MOVLW
0x07 ADCON1 0x05
MOVWF
TRISE
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Preliminary
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PIC18FXX39
REGISTER 9-1: TRISE REGISTER
R-0 IBF bit 7 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode Unimplemented: Read as '0' TRISE2: RE2 Direction Control bit 1 = Input 0 = Output TRISE1: RE1 Direction Control bit 1 = Input 0 = Output TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 TRISE2 R/W-1 TRISE1 R/W-1 TRISE0 bit 0
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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PIC18FXX39
TABLE 9-9:
Name
PORTE FUNCTIONS
Bit# Buffer Type Function Input/output port pin or analog input or read control input in Parallel Slave Port mode For RD (PSP mode): 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected). Input/output port pin or analog input or write control input in Parallel Slave Port mode For WR (PSP mode): 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected). Input/output port pin or analog input or chip select control input in Parallel Slave Port mode For CS (PSP mode): 1 = Device is not selected 0 = Device is selected
RE0/AN5/RD
bit0
ST/TTL(1)
RE1/AN6/WR
bit1
ST/TTL(1)
RE2/AN7/CS
bit2
ST/TTL(1)
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 9-10:
Name PORTE LATE TRISE ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 6 -- -- OBF ADCS2 Bit 5 -- -- IBOV -- Bit 4 -- -- PSPMODE -- Bit 3 -- -- -- PCFG3 Bit 2 RE2 Bit 1 RE1 Bit 0 RE0 Value on POR, BOR ---- -000 ---- -xxx 0000 -111 00-- 0000 Value on All Other RESETS ---- -000 ---- -uuu 0000 -111 00-- 0000
Bit 7 -- -- IBF ADFM
LATE Data Output Register PORTE Data Direction bits PCFG2 PCFG1 PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTE.
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Preliminary
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PIC18FXX39
9.6 Parallel Slave Port
FIGURE 9-10:
The Parallel Slave Port is implemented on the 40-pin devices only (PIC18F4X39). PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. It is asynchronously readable and writable by the external world through RD control input pin, RE0/AN5/RD and WR control input pin, RE1/AN6/WR. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/AN5/RD to be the RD input, RE1/AN6/WR to be the WR input and RE2/AN7/ CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). The A/D port configuration bits, PCFG2:PCFG0 (ADCON1<2:0>), must be set, which will configure pins RE2:RE0 as digital I/O. A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs), and the ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL.
PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
Data Bus
D CK
Q
WR LATD or PORTD
RDx Pin TTL
Data Latch Q D EN EN TRIS Latch
RD PORTD
RD LATD
One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>)
Read
TTL
RD CS WR
Chip Select TTL Write TTL
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 9-11:
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
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PIC18FXX39
FIGURE 9-12: PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
TABLE 9-11:
Name PORTD LATD TRISD PORTE LATE TRISE INTCON PIR1 PIE1 IPR1 ADCON1 Bit 7
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 -- -- PSPMODE INT0IE TXIF TXIE TXIP -- -- -- -- RBIE SSPIF SSPIE SSPIP PCFG3 RE2 RE1 RE0 ---- -000 ---- -xxx 0000 -111 0000 000x 0000 0000 0000 0000 0000 0000 00-- 0000 RBIF TMR1IF TMR1IE TMR1IP PCFG0 LATE Data Output bits PORTE Data Direction bits TMR0IF -- -- -- PCFG2 INT0IF TMR2IF TMR2IE TMR2IP PCFG1 -- -- IBOV TMR0IF RCIF RCIE RCIP -- Value on All Other RESETS uuuu uuuu uuuu uuuu 1111 1111 ---- -000 ---- -uuu 0000 -111 0000 000u 0000 0000 0000 0000 0000 0000 00-- 0000
Port Data Latch when written; Port pins when read LATD Data Output bits PORTD Data Direction bits -- -- IBF GIE/ GIEH PSPIF PSPIE PSPIP ADFM -- -- OBF PEIE/ GIEL ADIF ADIE ADIP ADCS2
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.
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Preliminary
DS30485A-page 97
PIC18FXX39
NOTES:
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PIC18FXX39
10.0 TIMER0 MODULE
The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock Figure 10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 10-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 10-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection.
REGISTER 10-1:
T0CON: TIMER0 CONTROL REGISTER
R/W-1 TMR0ON bit 7 R/W-1 T08BIT R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0
bit 7
TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2-0
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Preliminary
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PIC18FXX39
FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus FOSC/4 0 1 1 RA4/T0CKI pin T0SE 3 T0PS2, T0PS1, T0PS0 T0CS PSA Programmable Prescaler 0 Sync with Internal Clocks (2 TCY delay) Set Interrupt Flag bit TMR0IF on Overflow 8 TMR0L
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 10-2:
FOSC/4
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
0 1 1 Sync with Internal Clocks (2 TCY delay) TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow
T0CKI pin T0SE
Programmable Prescaler 3
0
Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0>
T0CS PSA T0PS2, T0PS1, T0PS0
Note:
Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
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PIC18FXX39
10.1 Timer0 Operation
10.2.1
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0L register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control; it can be changed "on-the-fly" during program execution.
10.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IE bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP.
10.4
16-bit Mode Timer Reads and Writes
10.2
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values in power-of-2 increments, from 1:2 through 1:256, are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0L register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0,etc.) will clear the prescaler count. Note: Writing to TMR0L when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (see Figure 10-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.
TABLE 10-1:
Name TMR0L TMR0H INTCON T0CON TRISA
REGISTERS ASSOCIATED WITH TIMER0
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx 0000 0000 INT0IE T0SE RBIE PSA TMR0IF T0PS2 INT0IF T0PS1 RBIF T0PS0 0000 000x 1111 1111 -111 1111 Value on All Other RESETS uuuu uuuu 0000 0000 0000 000u 1111 1111 -111 1111
Bit 7
Timer0 Module Low Byte Register Timer0 Module High Byte Register GIE/GIEH TMR0ON -- PEIE/GIEL T08BIT TMR0IE T0CS
PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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Preliminary
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PIC18FXX39
NOTES:
DS30485A-page 102
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
11.0 TIMER1 MODULE
The Timer1 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers, TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h Figure 11-1 is a simplified block diagram of the Timer1 module. Register 11-1 details the Timer1 control register, which sets the Operating mode of the Timer1 module. Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON<0>).
REGISTER 11-1:
T1CON: TIMER1 CONTROL REGISTER
R/W-0 RD16 bit 7 U-0 -- R/W-0 T1CKPS1 R/W-0 T1CKPS0 U-0 -- R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
bit 7
RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value Unimplemented: Maintain as '0' T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6 bit 5-4
bit 3 bit 2
bit 1
bit 0
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Preliminary
DS30485A-page 103
PIC18FXX39
11.1 Timer1 Operation
Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The Operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input.
FIGURE 11-1:
TMR1IF Overflow Interrupt Flag bit
TIMER1 BLOCK DIAGRAM
Synchronized Clock Input
TMR1 TMR1H TMR1L TMR1ON On/Off
0 1 T1SYNC Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS
T13CKI FOSC/4 Internal Clock
1
Synchronize det SLEEP Input
FIGURE 11-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0> 8
TMR1H
8 Write TMR1L Read TMR1L TMR1IF Overflow Interrupt Flag bit 8 Timer 1 High Byte TMR1
8
0 TMR1L TMR1ON on/off 1 T1SYNC Prescaler 1, 2, 4, 8 0 TMR1CS T1CKPS1:T1CKPS0 2
Synchronized Clock Input
T13CKI FOSC/4 Internal Clock
1
Synchronize det SLEEP Input
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PIC18FXX39
11.2 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). the user with the ability to accurately read all 16-bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.
11.3
Timer1 16-bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes (see Figure 11-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides
TABLE 11-1:
Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON Legend: Bit 7
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF -- -- -- Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on All Other RESETS
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP
(1)
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
ADIF ADIE ADIP
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register RD16 -- T1CKPS1 T1CKPS0 --
T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
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Preliminary
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PIC18FXX39
NOTES:
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Preliminary
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PIC18FXX39
12.0 TIMER2 MODULE
Note: The Timer2 module is an 8-bit timer with a selectable 8-bit period. It has the following features: * Input from system clock at FOSC/4 with programmable input prescaler * Interrupt on timer-to-period match with programmable postscaler The module has three registers: the TMR2 counter, the PR2 period register, and the T2CON control register. The general operation of Timer2 is shown in Figure 12-1. Additional information on the use of Timer2 as a time-base is available in Section 15.0 (PWM Modules). In PIC18FXX39 devices, Timer2 is used exclusively as a time-base for the PWM modules in motor control applications. As such, it is not available to users as a resource. Although their locations are shown on the device data memory maps, none of the Timer2 registers are directly accessible. Users should not alter the values of these registers.
FIGURE 12-1:
TIMER2 BLOCK DIAGRAM
FOSC/4
Prescaler 1:1, 1:4, 1:16
TMR2 RESET (TMR2 = PR2) Comparator Postscaler 1:1 to 1:16
TMR2 Output
(ProMPT Module)
Sets Flag bit TMR2IF
PR2
(ProMPT Module)
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PIC18FXX39
NOTES:
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
13.0 TIMER3 MODULE
The Timer3 module timer/counter has the following features: * 16-bit timer/counter (two 8-bit registers: TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt-on-overflow from FFFFh to 0000h Figure 13-1 is a simplified block diagram of the Timer3 module. Register 13-1 shows the Timer1 control register, which sets the Operating mode of the Timer1 module.
REGISTER 13-1:
T3CON: TIMER3 CONTROL REGISTER
R/W-0 RD16 bit 7 R/W-0 -- R/W-0 R/W-0 R/W-0 -- R/W-0 T3SYNC R/W-0 TMR3CS R/W-0 TMR3ON bit 0 T3CKPS1 T3CKPS0
bit 7
RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer3 in one 16-bit operation 0 = Enables register read/write of Timer3 in two 8-bit operations Unimplemented: Maintain as `0' T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from T13CKI (on the rising edge after the first falling edge) 0 = Internal clock (FOSC/4) TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6, 3 bit 5, 4
bit 2
bit 1
bit 0
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Preliminary
DS30485A-page 109
PIC18FXX39
13.1 Timer3 Operation
Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The Operating mode is determined by the clock select bit, TMR3CS (T3CON<1>). When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input.
FIGURE 13-1:
TIMER3 BLOCK DIAGRAM
TMR3IF Overflow Interrupt Flag bit TMR3H TMR3L TMR3ON On/Off
0 1 T3SYNC
Synchronized Clock Input
T13CKI FOSC/4 Internal Clock
1 Prescaler 1, 2, 4, 8 0 2 TMR3CS T3CKPS1:T3CKPS0
Synchronize det SLEEP Input
FIGURE 13-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
Data Bus<7:0> 8 TMR3H 8 Write TMR3L Read TMR3L Set TMR3IF Flag bit on Overflow 8 Timer3 High Byte TMR3 TMR3L 1 TMR3ON On/Off T13CKI FOSC/4 Internal Clock To Timer1 Clock Input 1 Prescaler 1, 2, 4, 8 0 2 T3SYNC Synchronize det SLEEP Input 0 Synchronized Clock Input 8
T3CKPS1:T3CKPS0 TMR3CS
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PIC18FXX39
13.2 Timer3 Interrupt
The TMR3 Register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR3IF (PIR2<1>). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit, TMR3IE (PIE2<1>).
TABLE 13-1:
Name INTCON PIR2 PIE2 IPR2 TMR3L TMR3H T1CON T3CON Legend:
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
Bit 6 Bit 5 TMR0IE -- -- -- Bit 4 INT0IE EEIF EEIE EEIP Bit 3 RBIE BCLIF BCLIE BCLIP Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 RBIF -- -- -- Value on POR, BOR Value on All Other RESETS
Bit 7
GIE/GIEH PEIE/GIEL -- -- -- -- -- --
0000 000x 0000 000u ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register Holding Register for the Most Significant Byte of the 16-bit TMR3 Register RD16 RD16 -- -- T1CKPS1 T1CKPS0 T3CKPS1 T3CKPS0 -- -- T1SYNC T3SYNC
TMR1CS TMR1ON 0-00 0000 u-uu uuuu TMR3CS TMR3ON 0000 0000 uuuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
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14.0 SINGLE PHASE INDUCTION MOTOR CONTROL KERNEL
ratio, the motor's speed can be varied with constant current. Maintaining this constant ratio is the function of the Motor Control kernel.
The Motor Control kernel of the PIC18FXX39 family uses Programmable Motor Processor Technology (ProMPT) to control the speed of a single phase induction motor, with variable frequency technology. The controller's two PWM modules are used to synthesize a sine wave current through the motor windings. The kernel provides open loop control for a continuous frequency range of 15 Hz to 127 Hz.
EQUATION 14-1:
Vx or: V 2f V I -f where: V I f
KEY RELATIONSHIPS IN SINGLE PHASE MOTORS
(1-1) (1-2) (1-3)
14.1
Theory of Operation
The speed of an induction motor is a function of frequency, slip and the number of poles in the motor. They are related by the equation: Speed = ( F x 120 P ) - Slip where Speed and Slip are in RPM, F is the frequency of the input voltage (in Hertz), and P represents the number of motor poles (for this equation, either 2, 4, 6 or 8). For the purpose of this discussion, slip is assumed to be constant across the motor's useful operating range. Since the rated speed is based on the number of poles (which is fixed at the time of manufacture), this leaves changing the frequency of the supplied voltage as the only way to vary the motor's speed. When the frequency controlling a motor is reduced, however, its impedance is also reduced, resulting in a higher motor current draw. It can be shown that the voltage applied to the motor is proportional to both the frequency and the current (Equation 14-1). So to keep the current constant at, or below the Full Load Amp rating, the RMS voltage to the motor must be reduced as the frequency is reduced. By varying the supply voltage and frequency at a constant
is applied voltage is motor current is stator flux is input frequency
14.2
Typical Hardware Interface
A block diagram for a recommended single phase induction motor control using the PIC18FXX39 is shown in Figure 14-1. The single phase AC supply is rectified, using a diode bridge and filtered, using a capacitor. The PWM outputs from the PIC18FXX39 synthesize the AC to drive the motor from this DC bus by switching Insulated Gate Bipolar Transistors (IGBTs) on and off. The IGBT gate driver converts the TTL level of PWMs to the required IGBT gate voltage level, and supplies the gate charging current when the IGBT turns on. The I/O ports of the microcontroller can be used for the external logic controls. The A/D channels can be used for monitoring the DC bus voltage and motor current; a potentiometer can also be connected to one of these channels to provide a variable frequency reference for the motor.
FIGURE 14-1:
TYPICAL MOTOR CONTROL SYSTEM USING THE PIC18FXX39
Single Phase AC Input L N G
MOV
Rectifier
+
+15V Power Supply +5V GND
Voltage Monitor A/D PWM1 PWM2 A/D Gate Drives
I/OPorts Digital PIC18FXX39 I/O Interface A/D Analog
M1 IGBT Driver M2 IGBT H-Bridge G Motor
Current Monitor
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14.3 Software Interface
A sine table, stored in the ProMPT kernel, is used as the basis for synthesizing the DC bus using the PWM modules. The table values are accessed in sequence and scaled based on the frequency or the speed at which the motor is intended to run. The intended frequency input can be from an A/D channel or a digital value. Parameters in the ProMPT modules can be accessed using the pre-defined Application Program Interface (API) methods. A list of the APIs is given in Section 14.3.3. For example, to run the motor at 40 Hz, the user would invoke the PromMPT_SetFrequency API: i = ProMPT_SetFrequency(40); where i is an unsigned character variable. In this case, if i = 0 on return, the command has been successfully executed. If the frequency input is out of range, or if there is an error in setting the frequency, i is returned with a value of FFh. Similarly, to check the frequency set by the ProMPT kernel, use the ProMPT_GetFrequency API: i = ProMPT_GetFrequency(void); where i is an unsigned character variable. Upon return from the ProMPT kernel, i will contain the frequency value in the ProMPT kernel. Acceleration rate: The rate of increase of motor speed, achieved by ramping up the supply frequency. Expressed in Hz/s. Deceleration rate: The rate of decrease of motor speed, achieved by ramping down the supply frequency. Expressed in Hz/s. Boost: The mode for starting a stopped motor by varying the supply current frequency and modulation until steady state speed is reached. Boost is defined in terms of a frequency, a starting and ending modulation, and a time interval for the transition between the two. PWM Frequency: The sampling rate (in kHz) at which the PWM module operates.
FIGURE 14-2:
150 Voltage Modulation (%) 125 100 75 50 25 0 0 20 40
DEFAULT V/F CURVE FOR THE ProMPT KERNEL
Vrated of motor should equal at 100% modulation
frated of motor should equal f at 100% modulation
14.3.1
THE V/F CURVE
60
80
100
120
140
The ProMPT kernel contains a default V/F curve stored in memory. The default curve is linear, as shown in Figure 14-2. Table 14-1 shows the data points used to construct the curve. Users may require a different V/F curve for their application, based on the load on the motor, or based on the characteristics of the motor used. The curve can be changed in the application program using the API method SetVFCurve(X,Y), where X is the frequency and Y is the level of modulation of the DC bus voltage. As a rule, in customizing the curve, the input frequency corresponding to the point on the V/F curve that gives 100% modulation should match the motor's rated frequency. Similarly, full modulation should occur at the motor's rated input voltage. (See Figure 14-2 for details.) Examples of the characteristics for V/F curves for typical motor applications are shown in Section 14-2 (page 115).
Input Frequency (Hz)
TABLE 14-1:
DATA POINTS FOR THE DEFAULT V/F CURVE
% Modulation 0 14 28 42 57 71 86 100 110 133 133 133 133 133 133 133 133
Frequency (Hz) 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128
14.3.2
PARAMETERS DEFINED BY THE ProMPT API METHODS
Frequency: The frequency (in Hz) of the supply current for steady state motor operation. Modulation: The level of modulation (in percentage) applied to the DC supply voltage by the PWM through the H-bridge to produce AC drive current.
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TABLE 14-2: ProMPT OUTPUT CHARACTERISTICS FOR VARIOUS V/F CURVES
Shaded Pole Blower 115V 3.5/3.25A 50/60 Hz 1570 RPM 1/10 HP Measured Frequency (Hz) Deviation (%) Measured Output Voltage (RMS) 22.8 28.2 33.5 42.0 52.6 62.0 72.3 81.3 90.7 99.6 107.8 112.3 111.5 111.3 15.0 18.4 21.4 29.5 36.6 44.7 53.9 62.9 73.4 88.2 102.0 108.8 108.0 109.1 Measured Output Current (A) 1.59 1.75 1.92 2.08 2.26 2.40 2.57 2.70 2.79 2.96 3.10 3.26 3.53 3.69 1.00 1.10 1.23 1.44 1.60 1.79 2.01 2.21 2.47 2.79 3.05 3.25 3.50 3.58 Motor Speed (RPM) Motor Type: Rated Voltage: Full Load Current: Rated Frequency: Rated Speed: Rated Power: Input Frequency (Hz)
Linear V/F Curve (Pre-programmed) 15 18 20 25 30 35 40 45 50 55 60 65 70 75 15 18 20 25 30 35 40 45 50 55 60 65 70 75 14.8 17.8 19.8 24.7 29.7 34.6 39.6 44.5 49.5 54.4 59.4 64.3 69.3 74.2 14.8 17.8 19.8 24.7 29.7 34.6 39.6 44.5 49.5 54.4 59.4 64.3 69.3 74.3 1.3 1.1 1.0 1.2 1.0 1.1 1.0 1.1 1.0 1.1 1.0 1.1 1.0 1.1 1.3 1.1 1.0 1.2 1.0 1.1 1.0 1.1 1.0 1.1 1.0 1.1 1.0 0.9 348 445 505 651 794 926 1060 1185 1305 1421 1536 1565 1450 1070 3.5 396 456 602 722 852 979 1092 1221 1367 1488 1538 1385 994
Pump V/F Curve
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TABLE 14-2: ProMPT OUTPUT CHARACTERISTICS FOR VARIOUS V/F CURVES (CONTINUED)
Shaded Pole Blower 115V 3.5/3.25A 50/60 Hz 1570 RPM 1/10 HP Measured Frequency (Hz) Deviation (%) Measured Output Voltage (RMS) 6.2 8.5 11.3 17.3 24.0 31.5 38.9 49.5 61.6 73.5 93.8 106.8 108.9 109.5 14.9 19.1 23.5 32.8 41.2 51.5 62.2 73.7 83.0 92.5 103.5 108.0 107.8 108.1 Measured Output Current (A) 0.45 0.57 0.69 0.94 1.17 1.43 1.66 1.96 2.26 2.56 2.94 3.24 3.49 3.58 0.99 1.15 1.31 1.56 1.79 2.01 2.23 2.47 2.64 2.86 3.06 3.22 3.50 3.55 Motor Speed (RPM) Motor Type: Rated Voltage: Full Load Current: Rated Frequency: Rated Speed: Rated Power: Input Frequency (Hz)
Strong Fan V/F Curve 15 18 20 25 30 35 40 45 50 55 60 65 70 75 15 18 20 25 30 35 40 45 50 55 60 65 70 75 14.8 17.8 19.8 24.7 29.7 34.6 39.6 44.5 49.5 54.4 59.4 64.3 69.3 74.2 14.8 17.8 19.8 24.7 29.7 34.6 39.6 44.5 49.4 54.4 59.4 64.3 69.3 74.2 1.3% 1.1% 1.0% 1.2% 1.0% 1.1% 1.0% 1.1% 1.0% 1.1% 1.0% 1.1% 1.0% 1.1% 1.3% 1.1% 1.0% 1.2% 1.0% 1.1% 1.0% 1.1% 1.2% 1.1% 1.0% 1.1% 1.0% 1.1% 100 193 264 408 538 654 720 888 1040 1162 1410 1534 1401 1016 306 405 475 619 759 893 1018 1155 1277 1397 1498 1500 1348 949
Weak Fan V/F Curve
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14.3.3
Note:
ProMPT API METHODS
The operation of the Motor Control kernel and its APIs is based on an assumed clock frequency of 20 MHz. Changing the oscillator frequency will change the timing used in the Motor Control kernel accordingly. To achieve the best results in motor control applications, a clock frequency of 20 MHz is highly recommended.
There are 27 separate API methods for the ProMPT kernel:
void ProMPT_ClearTick(void) Resources used: 0 stack levels Description: This function clears the Tick (62.5 ms) timer flag returned by ProMPT_tick(). This function must be called by any routine that is used for timing purposes. void ProMPT_DisableBoostMode(void) Resources used: 0 stack levels Description: This function disables the Boost mode logic. This method should be called before changing any of the Boost mode parameters. void ProMPT_EnableBoostMode(void) Resources used: 0 stack levels Description: This function enables the Boost mode logic. Boost mode is entered when a stopped drive is commanded to start. The drive will immediately go to Boost Frequency and ramp from Start Modulation to End Modulation over the time period, Boost Time. unsigned char ProMPT_GetAccelRate(void) Resources used: 1 stack level Range of values: 0 to 255 Description: Returns the current Acceleration Rate in Hz/second. unsigned char ProMPT_GetBoostEndModulation(void) Resources used: 1 stack level Range of values: 0 to 200 Description: Returns the current End Modulation (in %) used in the boost logic. unsigned char ProMPT_GetBoostFrequency(void) Resources used: 1 stack level Range of values: 0 to 127 Description: Returns the current Boost Frequency in Hz. unsigned char ProMPT_GetBoostStartModulation(void) Resources used: 1 stack level Range of values: 0 to BoostEndModulation Description: Returns the Start Modulation (in %) used in the Boost logic.
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unsigned char ProMPT_GetBoostTime() Resources used: 1 stack level Range of values: 0 to 255 Description: Returns the time in seconds for Boost mode. unsigned char ProMPT_GetDecelRate() Resources used: 1 stack level Range of values: 0 to 255 Description: Returns the current deceleration rate in Hz/second. unsigned char ProMPT_GetFrequency(void) Resources used: 1 stack level Range of values: 0 to 127 Description: Returns the current output frequency in Hz. This may not be the frequency commanded due to Boost or Accel/Decel logic. unsigned char ProMPT_GetModulation(void) Resources used: Hardware Multiplier; 1 stack level Range of values: 0 to 200 Description: Returns the current output modulation in %. unsigned char ProMPT_GetParameter(unsigned char parameter) Resources used: 1 stack level Description: In addition to its pre-defined API methods, the ProMPT kernel allows the user to custom define up to 16 functions for control or communication purposes not covered by the ProMPT APIs. These parameters are used to communicate with motor control GUI evaluation tools, such as Microchip's DashDriveMPTM. This method returns the current value of any one of the parameters. unsigned char ProMPT_GetVFCurve(unsigned char point) Resources used: Hardware Multiplier; 1 stack level Description: This function returns one of the 17 modulation values (in %) of the V/F curve. Each point represents a frequency increment of 8 Hz, ranging from point 0 (0 Hz) to point 16 (128 Hz). void ProMPT_Init(unsigned char PWMfrequency) Resources used: 64 Bytes RAM; Timer2; PWM1 and PWM2; High Priority Interrupt Vector; Hardware Multiplier; fast call/return; FSR 0; TBLPTR; 2 stack levels PWMfrequency values: 0 or 1 Description: This function must be called before all other ProMPT methods, and it must be called only once. This routine configures Timer2 and the PWM outputs. When PWMfrequency is `0', the module's operating frequency is 9.75 kHz. When PWMfrequency is `1', the module's operating frequency is 19.53 kHz. Note: Since the high priority interrupt is used, the fast call/return cannot be used by other routines.
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void ProMPT_SetAccelRate(unsigned char rate) Resources used: 0 stack level rate range: 0 to 255 Description: Sets the acceleration to the value of rate in Hz/second. The default setting is 10 Hz/s. void ProMPT_SetBoostEndModulation(unsigned char modulation) Resources used: Hardware Multiplier; 0 stack levels modulation range: 0 to 200 Description: Sets the End Modulation (in %) for the Boost logic. Boost mode operates at Boost Frequency, and the modulation ramps from BoostStartModulation to BoostEndModulation. This function should not be called while Boost is enabled. unsigned char ProMPT_SetBoostFrequency(unsigned char frequency) Resources used: 0 stack levels frequency range: 0 to 127 Description: Sets the frequency the drive goes to in Boost mode. Frequency must be < 128. On exit, w = 0 if the command is successful, or w = FFh if the frequency is out of range. This function should not be called while Boost is enabled. void ProMPT_SetBoostStartModulation(unsigned char modulation) Resources used: Hardware Multiplier; 0 stack levels modulation range: 0 to BoostEndModulation Description: Sets the Start Modulation (in %) for the Boost logic. Boost mode operates at Boost Frequency, and the modulation ramps from BoostStartModulation to BoostEndModulation. This function should not be called while Boost is enabled. void ProMPT_SetBoostTime(unsigned char time) Resources used: Hardware Multiplier; 0 stack levels time range: 0 to 255 Description: Sets the amount of time in seconds for the Boost mode. Boost mode operates at Boost Frequency, and the modulation ramps from BoostStartModulation to BoostEndModulation over BoostTime. This function should not be called while Boost is enabled. void ProMPT_SetDecelRate(unsigned char rate) Resources used: 0 stack levels rate range: 0 to 255 Description: Sets the deceleration to the value of rate in Hz per second. The default setting is 5 Hz/s. unsigned char ProMPT_SetFrequency(unsigned char frequency) Resources used: 2 stack levels frequency range: 0 to 127 Description: Sets the output frequency of the drive if the drive is running. Frequency is limited to 0 to 127, but should be controlled within the valid operational range of the motor. Modulation is determined from the V/F curve, which is set up with the ProMPT_SetVFCurve method. If frequency = 0, the drive will stop. If the drive is stopped and frequency > 0, the drive will start.
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void ProMPT_SetLineVoltage(unsigned char voltage) Resources used: Hardware Multiplier; 0 stack levels voltage range: 0 to 255 Description: Sets the line voltage for Automatic Voltage Compensation. The units for SetLineVoltage and SetMotorVoltage must be the same for accurate operation. The values passed to SetMotorVoltage and SetLineVoltage can be the same to disable voltage compensation. void ProMPT_SetMotorVoltage(unsigned char voltage) Resources used: Hardware Multiplier; 0 stack levels voltage range: 0 to 255 Description: Sets the motor rating for Automatic Voltage Compensation. The units for SetLineVoltage and SetMotorVoltage must be the same for accurate operation. The values passed to SetMotorVoltage and SetLineVoltage can be the same to disable voltage compensation. void ProMPT_SetParameter(unsigned char parameter, unsigned char value) Resources used: 0 stack levels parameter range: Description: In addition to its pre-defined API methods, the ProMPT kernel allows the user to custom define up to 16 functions for control or communication purposes not covered by the ProMPT APIs. This function sets the value of the specified user defined function. void ProMPT_SetPWMfrequency(unsigned char PWMfrequency) PWMfrequency values: 0 or 1 Resources used: Timer2; 1 stack level Description: This sets and changes the PWM switching frequency. Typically, this is set with the Init() function. When PWMfrequency is `0', the module's operating frequency is 9.75 kHz. When PWMfrequency is `1', the module's operating frequency is 19.53 kHz. void ProMPT_SetVFCurve(unsigned char point, unsigned char value) Resources used: Hardware Multiplier; 0 stack level point range: 0 to 16 (0 = 0 Hz, 1 = 8 Hz, 2 = 16 Hz....... 17 = 128 Hz) value range: 0 to 200 Description: This sets one of the 17 modulation values (in %) for the V/F curve. Each point represents a frequency increment of 8 Hz, ranging from point 0 (0 Hz) to point 16 (128 Hz). unsigned char ProMPT_Tick(void) Resources used: 1 stack level Description: The value of the Tick timer flag becomes `1' every 62.5 ms (1/16 second). This can be used for timing applications. clearTick must be called in the timing routine when this is serviced.
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14.4 Developing Applications Using the Motor Control Kernel
FIGURE 14-3: LAYERS OF THE MOTOR CONTROL ARCHITECTURE STACK
Application Software and User Interface
The Motor Control kernel allows users to develop their applications without having knowledge of motor control. The key parameters of the motor control kernel can be set and read through the Application Program Interface (API) methods discussed in the previous section. The overall application can be thought of as a protocol stack, as shown in Figure 14-3. In this case, the API methods reside between the user's application and the ProMPT kernel, and are used to exchange parameter values. The motor control kernel sets the PWM duty cycles based on the inputs from the application software. A typical motor control routine is shown in Example 14-1. In this case, the motor will run at 20 Hz for 10 seconds, accelerate to 60 Hz at the rate of 10 Hz/s, remain at 60 Hz for 20 seconds, and finally stop.
Application Program Interface (API) Methods Parameters
ProMPT Motor Control Kernel
Hardware
EXAMPLE 14-1:
MOTOR CONTROL ROUTINE USING THE ProMPT APIs
Void main() { unsigned char i; unsigned char j; ProMPT_Init(0); i = ProMPT_SetFrequency(10); for (i=0;i<161;i++) { j = ProMPT_Tick(void); ProMPT_ClearTick(void); } ProMPT_SetAccelRate(10); i = ProMPT_SetFrequency(60); for (i=0;i<161;i++) { j = ProMPT_Tick(void); ProMPT_ClearTick(void); j = ProMPT_Tick(void); ProMPT_ClearTick(void); } i = ProMPT_SetFrequency(0); while(1); }
// Initialize the ProMPT block // Set motor frequency to 10Hz // Set counter for 10 sec @ 1/16 sec per tick // Tick of 1/16 sec // Clearing the Tick flag
// Set acceleration rate to 10 Hz/sec // Set motor frequency to 60 Hz // // // // // // Set counter for 20 Sec @ 1/16 sec per tick (2 loops of 10 Sec each) Tick of 1/16 Sec Clearing the Tick flag Tick of 1/16 Sec Clearing the Tick flag
// Set motor frequency to 0 Hz (stop) // End of the task
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15.0 PULSE WIDTH MODULATION (PWM) MODULES
FIGURE 15-2:
Period
PWM OUTPUT
PIC18FXX39 devices are equipped with two 10-bit PWM modules. Each contains a register pair (CCPxH:CCPxL), which operates as a Master/Slave Duty Cycle register, and a control register (CCPxCON). The modules use Timer2 (Section 12.0) as their timebase reference. Figure 15-1 shows a simplified block diagram of the module's operation. This section gives a brief overview of PWM operation as controlled by the Motor Control module (Section 14.0). Operation is described with respect to PWM1, but is equally applicable to PWM2. Note: The PWM modules are used exclusively by the Motor Control module. As such, they are not available to users as a separate resource. Although their locations are shown on the device data memory maps, users should not modify the values of these registers.
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
15.1.1
PWM PERIOD
The PWM period is specified when the Motor Control module is initialized. The PWM period can be calculated using the formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. The API method void ProMPT_Init (page 118) sets the required PWM frequency in the application. The parameter PWMfrequency determines the operating frequency of the module. When it is `0', the PWM frequency set in the Motor Control module is 9.75 kHz; when it is `1', the set PWM frequency is 19.53 kHz. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The PWM1 pin is set (exception: if PWM duty cycle = 0%, the PWM1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 12.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
15.1
PWM Mode
In Pulse Width Modulation, each PWM pin produces a PWM output with a resolution of up to 10 bits. A PWM output (Figure 15-2) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 15-1:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H (Slave) Comparator TMR2 (1) R Q PWM1 S
Comparator PR2 Clear Timer, PWM1 pin and latch Duty Cycle
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler to create a 10-bit time-base.
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15.1.2 PWM DUTY CYCLE
The PWM duty cycle is set by the Motor Control module when it writes a 10-bit value to the CCPR1L and CCP1CON registers, where CCPR1L contains the eight Most Significant bits and CCP1CON<5:4> contains the two Least Significant bits. The duty cycle time is given by the equation: PWM duty cycle = (10-bit CCP register value) * TOSC * (TMR2 prescale value) either an internal 2-bit Q clock, or 2 bits of the TMR2 prescaler. When the CCPR1H:latch pair value matches that of the TMR2:latch pair, the PWM1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: FOSC log --------------- FPWM PWM Resolution (max) = -----------------------------bits log ( 2 ) where FPWM is the PWM frequency, or (1/PWM period). Note: If the PWM duty cycle value is longer than the PWM period, the PWM1 pin will not be cleared.
where TOSC and the duty cycle are in the same unit of time. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This buffering is essential for glitchless PWM operation. At the same time, the value of TMR2 is concatenated with
TABLE 15-1:
Name INTCON PIR1 PIE1 IPR1 TMR2 PR2* T2CON
* *
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP * * * * * * * Bit 4 INT0IE TXIF TXIE TXIP * * * * * * * Bit 3 RBIE SSPIF SSPIE SSPIP * * * * * * * Bit 2 TMR0IF -- -- -- * * * * * * * Bit 1 INT0IF TMR2IF TMR2IE TMR2IP * * * * * * * Bit 0 RBIF Value on POR, BOR Value on All Other RESETS
GIE/GIEH PEIE/GIEL PSPIF(1) PSPIE(1) PSPIP(1) * * * * -- * -- ADIF ADIE ADIP * * * * -- * --
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 0000 0000 0000 0000 * * * * * * * 0000 0000 0000 0000 1111 1111 1111 1111 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000
CCPR1L* CCPR1H CCP1CON* CCPR2L
*
PWM Register1 (MSB) (read-only)
CCPR2H* CCP2CON* Legend:
PWM Register2 (MSB) (read-only)
x = unknown, u = unchanged, - = unimplemented, read as '0' unless otherwise noted. Shaded cells are not used by PWM and Timer2. * These registers are retained to maintain compatibility with PIC18FXX2 devices; however, the indicated bits are reserved in PIC18FXX39 devices. Users should not alter the values of these bits. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
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16.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE
Master SSP (MSSP) Module Overview 16.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) - RA5/AN4/SS/LVDIN Figure 16-1 shows the block diagram of the MSSP module when operating in SPI mode.
16.1
The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-Master mode * Slave mode
FIGURE 16-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF reg Write
16.2
Control Registers
The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2). The use of these registers and their individual configuration bits differ significantly, depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections.
RC4/SDI/SDA SSPSR reg RC5/SDO bit0 shift clock
RA5/AN4/SS/ LVDIN
SS Control Enable Edge Select 2 Clock Select
RC3/SCK/ SCL
SMP:CKE 2 Edge Select
SSPM3:SSPM0 4
/4 / 16 / 64
Prescaler
TOSC
Data to TX/RX in SSPSR TRIS bit
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16.3.1 REGISTERS
The MSSP module has four registers for SPI mode operation. These are: * * * * MSSP Control Register1 (SSPCON1) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not double-buffered. A write to SSPBUF will write to both SSPBUF and SSPSR.
SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation. The SSPCON1 register is readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write.
REGISTER 16-1:
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
R/W-0 SMP bit 7 R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
bit 7
SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode CKE: SPI Clock Edge Select bit When CKP = 0: 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK When CKP = 1: 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit Used in I2C mode only P: STOP bit Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared. S: START bit Used in I2C mode only R/W: Read/Write bit information Used in I2C mode only UA: Update Address Used in I2C mode only BF: Buffer Full Status bit (Receive mode only) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5 bit 4
bit 3 bit 2 bit 1 bit 0
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REGISTER 16-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE)
R/W-0 WCOL bit 7 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit SPI Slave mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow Note: bit 5 In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
bit 6
SSPEN: Synchronous Serial Port Enable bit 1 = Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit 1 = IDLE state for clock is a high level 0 = IDLE state for clock is a low level SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = Reserved 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note: Bit combinations not specifically listed here are either reserved, or implemented in I2C mode only.
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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16.3.2 OPERATION
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (IDLE state of SCK) Data input sample phase (middle or end of data output time) * Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then, the buffer full detect bit, BF (SSPSTAT<0>), and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the * * * * SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON1<7>), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 16-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT) indicates the various status conditions.
EXAMPLE 16-1:
LOADING THE SSPBUF (SSPSR) REGISTER
;Has data been received(transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit
LOOP BTFSS SSPSTAT, BF BRA LOOP MOVF SSPBUF, W MOVWF RXDATA MOVF TXDATA, W MOVWF SSPBUF
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16.3.3 ENABLING SPI I/O 16.3.4 TYPICAL CONNECTION
To enable the serial port, SSP Enable bit, SSPEN (SSPCON1<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI is automatically controlled by the SPI module * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * SS must have TRISC<4> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. Figure 16-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: * Master sends data -- Slave sends dummy data * Master sends data -- Slave sends data * Master sends dummy data -- Slave sends data
FIGURE 16-2:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb SDO SDI
SPI Slave SSPM3:SSPM0 = 010xb
Serial Input Buffer (SSPBUF)
Serial Input Buffer (SSPBUF)
Shift Register (SSPSR) MSb LSb
SDI
SDO
Shift Register (SSPSR) MSb LSb
SCK PROCESSOR 1
Serial Clock
SCK PROCESSOR 2
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16.3.5 MASTER MODE
The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 16-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "Line Activity Monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This then, would give waveforms for SPI communication as shown in Figure 16-3, Figure 16-5, and Figure 16-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: * FOSC/4 (or TCY) * FOSC/16 (or 4 * TCY) * FOSC/64 (or 16 * TCY) This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 16-3 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown.
FIGURE 16-3:
Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF SSPSR to SSPBUF
SPI MODE WAVEFORM (MASTER MODE)
4 Clock Modes
bit7 bit7
bit6 bit6
bit5 bit5
bit4 bit4
bit3 bit3
bit2 bit2
bit1 bit1
bit0 bit0
bit7
bit0
bit7
bit0
Next Q4 cycle after Q2
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16.3.6 SLAVE MODE
In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications. While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/ pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict.
16.3.7
SLAVE SELECT SYNCHRONIZATION
The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The Data Latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no
FIGURE 16-4:
SS
SLAVE SYNCHRONIZATION WAVEFORM
SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0)
Write to SSPBUF
SDO
bit7
bit6
bit7
bit0
SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
bit0 bit7 bit7
Next Q4 cycle after Q2
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FIGURE 16-5:
SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
bit7
bit0
Next Q4 cycle after Q2
FIGURE 16-6:
SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit7
bit0
Next Q4 cycle after Q2
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16.3.8 SLEEP OPERATION 16.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to Normal mode, the module will continue to transmit/ receive data. In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the device to be placed in SLEEP mode and data to be shifted into the SPI transmit/receive shift register. When all 8 bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device from SLEEP. Table 16-1 shows the compatibility between the standard SPI modes and the states the CKP and CKE control bits.
TABLE 16-1:
SPI BUS MODES
Control Bits State CKP 0 0 1 1 CKE 1 0 1 0
Standard SPI Mode Terminology 0, 0, 1, 1, 0 1 0 1
16.3.9
EFFECTS OF A RESET
A RESET disables the MSSP module and terminates the current transfer.
There is also an SMP bit which controls when the data is sampled.
TABLE 16-2:
Name INTCON PIR1 PIE1 IPR1 TRISC SSPBUF SSPCON TRISA SSPSTAT
REGISTERS ASSOCIATED WITH SPI OPERATION
Bit 7 Bit 6 PEIE/ GIEL ADIF ADIE ADIP TRISC6 SSPOV CKE Bit 5 TMR0IE RCIF RCIE RCIP TRISC5 SSPEN D/A Bit 4 INT0IE TXIF TXIE TXIP TRISC4 CKP P Bit 3 RBIE SSPIF SSPIE SSPIP TRISC3 SSPM3 S Bit 2 TMR0IF -- -- -- * SSPM2 R/W Bit 1 INT0IF TMR2IF TMR2IE TMR2IP * SSPM1 UA Bit 0 RBIF TMR1IF TMR1IE TMR1IP TRISC0 SSPM0 BF Value on POR, BOR Value on All Other RESETS
GIE/GIEH PSPIF(1) PSPIE(1) PSPIP(1) TRISC7 WCOL -- SMP
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 -111 1111 -111 1111 0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. * Reserved bits; do not modify. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices; always maintain these bits clear.
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16.4 I2C Mode
16.4.1 REGISTERS
The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master function). The MSSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer: * Serial clock (SCL) - RC3/SCK/SCL * Serial data (SDA) - RC4/SDI/SDA The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The MSSP module has six registers for I2C operation. These are: * * * * * MSSP Control Register1 (SSPCON1) MSSP Control Register2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) SSPCON, SSPCON2 and SSPSTAT are the control and status registers in I2C mode operation. The SSPCON and SSPCON2 registers are readable and writable. The lower 6 bits of the SSPSTAT are read only. The upper two bits of the SSPSTAT are read/write. SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. SSPADD register holds the slave device address when the SSP is configured in I2C Slave mode. When the SSP is configured in Master mode, the lower seven bits of SSPADD act as the baud rate generator reload value. In receive operations, SSPSR and SSPBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set. During transmission, the SSPBUF is not doublebuffered. A write to SSPBUF will write to both SSPBUF and SSPSR.
FIGURE 16-7:
MSSP BLOCK DIAGRAM (I2C MODE)
Internal Data Bus Read SSPBUF reg Shift Clock SSPSR reg Write
RC3/SCK/SCL
RC4/ SDI/ SDA
MSb
LSb
Match Detect
Addr Match
SSPADD reg START and STOP bit Detect Set, Reset S, P bits (SSPSTAT reg)
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REGISTER 16-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE)
R/W-0 SMP bit 7 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High Speed mode (400 kHz) CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs D/A: Data/Address bit In Master mode: Reserved In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit 1 = Indicates that a STOP bit has been detected last 0 = STOP bit was not detected last Note: This bit is cleared on RESET and when SSPEN is cleared. S: START bit 1 = Indicates that a START bit has been detected last 0 = START bit was not detected last Note: This bit is cleared on RESET and when SSPEN is cleared. R/W: Read/Write bit Information (I2C mode only) In Slave mode: 1 = Read 0 = Write Note: This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or not ACK bit. R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress Note: ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. bit 1 UA: Update Address (10-bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit In Transmit mode: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty In Receive mode: 1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
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REGISTER 16-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE)
R/W-0 WCOL bit 7 bit 7 R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode SSPEN: Synchronous Serial Port Enable bit 1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note: When enabled, the SDA and SCL pins must be properly configured as input or output.
bit 6
bit 5
bit 4
CKP: SCK Release Control bit In Slave mode: 1 = Release clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (Slave IDLE) 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1)) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address Note: Bit combinations not specifically listed here are either reserved, or implemented in SPI mode only.
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 16-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (Master Receive mode only) 1 = Not Acknowledge 0 = Acknowledge Note: bit 4 Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0
bit 6
bit 5
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only) 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence IDLE RCEN: Receive Enable bit (Master mode only) 1 = Enables Receive mode for I2C 0 = Receive IDLE PEN: STOP Condition Enable bit (Master mode only) 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition IDLE RSEN: Repeated START Condition Enabled bit (Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition IDLE SEN: START Condition Enabled/Stretch Enabled bit In Master mode: 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition IDLE In Slave mode: 1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled) 0 = Clock stretching is enabled for slave transmit only (Legacy mode) Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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16.4.2 OPERATION 16.4.3.1 Addressing
The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON1 register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * * * * I2C Master mode, clock = OSC/4 (SSPADD +1) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled * I 2C Firmware controlled master operation, slave is IDLE Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: 1. 2. 3. 4. The SSPSR register value is loaded into the SSPBUF register. The buffer full bit BF is set. An ACK pulse is generated. MSSP interrupt flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse.
Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. To ensure proper operation of the module, pull-up resistors must be provided externally to the SCL and SDA pins.
16.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). Slave mode hardware will always generate an The I interrupt on an address match. Through the mode select bits, the user can also choose to interrupt on START and STOP bits When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. Any combination of the following conditions will cause the MSSP module not to give this ACK pulse: * The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. * The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, are shown in timing parameter 100 and parameter 101.
2C
In 10-bit Address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `11110 A9 A8 0', where `A9' and `A8' are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. 2. Receive first (high) byte of Address (bits SSPIF, BF and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated START condition. Receive first (high) byte of Address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
16.4.3.2 Reception
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON1<6>) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. If SEN is enabled (SSPCON1<0> = 1), RC3/SCK/SCL will be held low (clock stretch) following each data transfer. The clock must be released by setting bit CKP (SSPCON<4>). See Section 16.4.4 ("Clock Stretching"), for more detail. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. In this case, when the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the START bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, pin RC3/SCK/SCL must be enabled by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse.
16.4.3.3
Transmission
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low, regardless of SEN (see "Clock Stretching", Section 16.4.4, for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RC3/ SCK/SCL should be enabled by setting bit CKP (SSPCON1<4>). The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 16-9).
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 139
FIGURE 16-8:
DS30485A-page 140
Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 R/W = 0 Receiving Data ACK Receiving Data D1 D0 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus Master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent.
PIC18FXX39
SDA
A7
A6
SCL
S
1
2
SSPIF
(PIR1<3>)
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS)
Preliminary
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
2002 Microchip Technology Inc.
CKP
(CKP does not reset to `0' when SEN = 0)
FIGURE 16-9:
2002 Microchip Technology Inc.
R/W = 1 ACK D1 D0 D4 D3 D5 D7 D6 A1 D3 D2 ACK D5 D4 D7 D6 D2 Transmitting Data Transmitting Data D1 D0 ACK A4 A2 A3 4 SCL held low while CPU responds to SSPIF 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software SSPBUF is written in software From SSPIF ISR Cleared in software SSPBUF is written in software From SSPIF ISR CKP is set in software CKP is set in software
Receiving Address
SDA
A7
A6
A5
SCL
S
1
2
3
Data in sampled
SSPIF (PIR1<3>)
I2C SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS)
Preliminary
BF (SSPSTAT<0>)
CKP
PIC18FXX39
DS30485A-page 141
FIGURE 16-10:
DS30485A-page 142
Clock is held low until update of SSPADD has taken place R/W = 0 ACK A7 D3 D2 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 A0 ACK Receive Second Byte of Address Receive Data Byte Receive Data Byte D1 D0 ACK Clock is held low until update of SSPADD has taken place 0 A9 A8 5 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 6 7 8 9 P Bus Master terminates transfer Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address
Receive First Byte of Address
PIC18FXX39
SDA
1
1
1
1
SCL
S
1
2
3
4
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)
Preliminary
SSPOV (SSPCON<6>)
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
2002 Microchip Technology Inc.
CKP
(CKP does not reset to `0' when SEN = 0)
FIGURE 16-11:
Bus Master terminates transfer Clock is held low until CKP is set to `1' R/W=1 ACK Transmitting Data Byte D7 D6 D5 D4 D3 D2 D1 D0 ACK
2002 Microchip Technology Inc.
Clock is held low until update of SSPADD has taken place R/W = 0 Receive Second Byte of Address Receive First Byte of Address ACK 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 1 0 A9 A8 Clock is held low until update of SSPADD has taken place 4 Sr 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag Write of SSPBUF BF flag is clear initiates transmit at the end of the third address sequence Completion of data transmission clears BF flag Cleared by hardware when SSPADD is updated with low byte of address UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with high byte of address CKP is set in software CKP is automatically cleared in hardware holding SCL low
Receive First Byte of Address
SDA
1
1
1
SCL
S
1
2
3
SSPIF
(PIR1<3>)
I2C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)
Preliminary
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
PIC18FXX39
CKP (SSPCON<4>)
DS30485A-page 143
PIC18FXX39
16.4.4 CLOCK STRETCHING 16.4.4.3
Both 7- and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence.
Clock Stretching for 7-bit Slave Transmit Mode
7-bit Slave Transmit mode implements clock stretching by clearing the CKP bit after the falling edge of the ninth clock, if the BF bit is clear. This occurs, regardless of the state of the SEN bit. The user's ISR must set the CKP bit before transmission is allowed to continue. By holding the SCL line low, the user has time to service the ISR and load the contents of the SSPBUF before the master device can initiate another transmit sequence (see Figure 16-9). Note 1: If the user loads the contents of SSPBUF, setting the BF bit before the falling edge of the ninth clock, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software, regardless of the state of the BF bit.
16.4.4.1
Clock Stretching for 7-bit Slave Receive Mode (SEN = 1)
In 7-bit Slave Receive mode, on the falling edge of the ninth clock at the end of the ACK sequence, if the BF bit is set, the CKP bit in the SSPCON1 register is automatically cleared, forcing the SCL output to be held low. The CKP being cleared to `0' will assert the SCL line low. The CKP bit must be set in the user's ISR before reception is allowed to continue. By holding the SCL line low, the user has time to service the ISR and read the contents of the SSPBUF before the master device can initiate another receive sequence. This will prevent buffer overruns from occurring (see Figure 16-13). Note 1: If the user reads the contents of the SSPBUF before the falling edge of the ninth clock, thus clearing the BF bit, the CKP bit will not be cleared and clock stretching will not occur. 2: The CKP bit can be set in software, regardless of the state of the BF bit. The user should be careful to clear the BF bit in the ISR before the next receive sequence, in order to prevent an overflow condition.
16.4.4.4
Clock Stretching for 10-bit Slave Transmit Mode
In 10-bit Slave Transmit mode, clock stretching is controlled during the first two address sequences by the state of the UA bit, just as it is in 10-bit Slave Receive mode. The first two addresses are followed by a third address sequence, which contains the high order bits of the 10-bit address and the R/W bit set to `1'. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode, and clock stretching is controlled by the BF flag, as in 7-bit Slave Transmit mode (see Figure 16-11).
16.4.4.2
Clock Stretching for 10-bit Slave Receive Mode (SEN = 1)
In 10-bit Slave Receive mode, during the address sequence, clock stretching automatically takes place but CKP is not cleared. During this time, if the UA bit is set after the ninth clock, clock stretching is initiated. The UA bit is set after receiving the upper byte of the 10-bit address, and following the receive of the second byte of the 10-bit address with the R/W bit cleared to `0'. The release of the clock line occurs upon updating SSPADD. Clock stretching will occur on each data receive sequence, as described in 7-bit mode. Note: If the user polls the UA bit and clears it by updating the SSPADD register before the falling edge of the ninth clock occurs, and if the user hasn't cleared the BF bit by reading the SSPBUF register before that time, then the CKP bit will still NOT be asserted low. Clock stretching on the basis of the state of the BF bit only occurs during a data sequence, not an address sequence.
DS30485A-page 144
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
16.4.4.5 Clock Synchronization and the CKP bit
If a user clears the CKP bit, the SCL output is forced to `0'. Setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. If the user attempts to drive SCL low, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set, and all other devices on the I2C bus have de-asserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 16-12).
FIGURE 16-12:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device asserts clock Master device de-asserts clock
WR SSPCON
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 145
FIGURE 16-13:
DS30485A-page 146
Clock is not held low because buffer full bit is clear prior to falling edge of 9th clock Clock is held low until CKP is set to `1' ACK Receiving Data D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 Receiving Address A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 R/W = 0 Receiving Data Clock is not held low because ACK = 1 ACK 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Bus Master terminates transfer Cleared in software SSPBUF is read SSPOV is set because SSPBUF is still full. ACK is not sent.
PIC18FXX39
SDA
A7
A6
SCL
S
1
2
SSPIF
(PIR1<3>)
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS)
Preliminary
If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to `0' and no clock stretching will occur BF is set after falling edge of the 9th clock, CKP is reset to `0' and clock stretching occurs
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
CKP CKP written to `1' in software
2002 Microchip Technology Inc.
FIGURE 16-14:
Clock is held low until update of SSPADD has taken place Clock is held low until CKP is set to `1' Receive Data Byte D1 D0 D7 D6 D5 D4 ACK D3 D2 D1 D0 R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 Receive Second Byte of Address Receive Data Byte
Clock is held low until update of SSPADD has taken place
Clock is not held low because ACK = 1 ACK
Receive First Byte of Address A9 A8
2002 Microchip Technology Inc.
6 1 2 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 3 4 5 6 7 8 9 P Cleared in software Cleared in software Cleared in software Bus Master terminates transfer Dummy read of SSPBUF to clear BF flag Dummy read of SSPBUF to clear BF flag SSPOV is set because SSPBUF is still full. ACK is not sent. Cleared by hardware when SSPADD is updated with low byte of address after falling edge of ninth clock UA is set indicating that SSPADD needs to be updated Note: Cleared by hardware when SSPADD is updated with high byte of address after falling edge of ninth clock An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA, and UA will remain set. Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA, and UA will remain set. CKP written to `1' in software
SDA
1
1
1
1
0
SCL
S
1
2
3
4
5
SSPIF
(PIR1<3>)
Cleared in software
BF (SSPSTAT<0>)
SSPBUF is written with contents of SSPSR
I2C SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS)
Preliminary
SSPOV (SSPCON<6>)
UA (SSPSTAT<1>)
UA is set indicating that the SSPADD needs to be updated
PIC18FXX39
CKP
DS30485A-page 147
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16.4.5 GENERAL CALL ADDRESS SUPPORT
The addressing procedure for the I2C bus is such that, the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all `0's with R/W = 0. The general call address is recognized when the General Call Enable bit (GCEN) is enabled (SSPCON2<7> set). Following a START bit detect, 8-bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPSTAT<1>). If the general call address is sampled when the GCEN bit is set, while the slave is configured in 10-bit Address mode, then the second half of the address is not necessary, the UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 16-15).
FIGURE 16-15:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS MODE)
Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving data D6 D5 D4 D3 D2 D1 D0 ACK
SDA SCL S SSPIF BF (SSPSTAT<0>)
General Call Address
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Cleared in software SSPBUF is read SSPOV (SSPCON1<6>) '0'
GCEN (SSPCON2<7>)
'1'
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Preliminary
2002 Microchip Technology Inc.
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16.4.6 MASTER MODE
Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set or the bus is IDLE, with both the S and P bits clear. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on START and STOP bit conditions. Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a START condition on SDA and SCL. Assert a Repeated START condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. Generate a STOP condition on SDA and SCL. The MSSP Module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to initiate transmission before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur.
The following events will cause SSP interrupt flag bit, SSPIF, to be set (SSP interrupt if enabled): * * * * * START condition STOP condition Data transfer byte transmitted/received Acknowledge Transmit Repeated START
FIGURE 16-16:
MSSP BLOCK DIAGRAM (I2C MASTER MODE)
Internal Data Bus Read SSPBUF Write Baud Rate Generator Clock Arbitrate/WCOL Detect (hold off clock source) DS30485A-page 149 Shift Clock SSPSR Receive Enable MSb LSb SSPM3:SSPM0 SSPADD<6:0>
SDA
SDA in
SCL
SCL in Bus Collision
START bit Detect STOP bit Detect Write Collision Detect Clock Arbitration State Counter for end of XMIT/RCV
Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2)
2002 Microchip Technology Inc.
Preliminary
Clock Cntl
START bit, STOP bit, Acknowledge Generate
PIC18FXX39
16.4.6.1 I2C Master Mode Operation
A typical transmit sequence would go as follows: 1. The user generates a START condition by setting the START enable bit, SEN (SSPCON2<0>). 2. SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. 3. The user loads the SSPBUF with the slave address to transmit. 4. Address is shifted out the SDA pin until all 8 bits are transmitted. 5. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 6. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 7. The user loads the SSPBUF with eight bits of data. 8. Data is shifted out the SDA pin until all 8 bits are transmitted. 9. The MSSP module shifts in the ACK bit from the slave device and writes its value into the SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a STOP condition by setting the STOP enable bit PEN (SSPCON2<2>). 12. Interrupt is generated once the STOP condition is complete. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition, or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic '0'. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for the SPI mode operation is used to set the SCL clock frequency for either 100 kHz, 400 kHz or 1 MHz I2C operation. See Section 16.4.7 ("Baud Rate Generator"), for more detail.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
16.4.7
I2C
BAUD RATE GENERATOR
In Master mode, the baud rate generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 16-17). When a write occurs to SSPBUF, the baud rate generator will automatically begin counting. The BRG counts down to `0' and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. Table 15-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD.
FIGURE 16-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0 SSPADD<6:0>
SSPM3:SSPM0 SCL
Reload Control CLKO
Reload
BRG Down Counter
FOSC/4
TABLE 16-3:
FCY
I2C CLOCK RATE W/BRG
FCY*2 20 MHz 20 MHz 20 MHz 8 MHz 8 MHz 8 MHz 2 MHz 2 MHz 2 MHz BRG Value 19h 20h 3Fh 0Ah 0Dh 28h 03h 0Ah 00h FSCL(2) (2 Rollovers of BRG) 400 kHz(1) 312.5 kHz 100 kHz 400 kHz(1) 308 kHz 100 kHz 333 kHz(1) 100kHz 1 MHz(1)
10 MHz 10 MHz 10 MHz 4 MHz 4 MHz 4 MHz 1 MHz 1 MHz 1 MHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. 2: Actual frequency will depend on bus conditions. Theoretically, bus conditions will add rise time and extend low time of clock period, producing the effective frequency.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 151
PIC18FXX39
16.4.7.1 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure 16-18).
FIGURE 16-18:
SDA
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
DX DX-1 SCL allowed to transition high
SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off)
03h
02h
SCL is sampled high, reload takes place and BRG starts its count BRG Reload
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
16.4.8 I2C MASTER MODE START CONDITION TIMING 16.4.8.1 WCOL Status Flag
To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the START condition and causes the S bit (SSPSTAT<3>) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2<0>) will be automatically cleared by hardware, the baud rate generator is suspended, leaving the SDA line held low and the START condition is complete. Note: If at the beginning of the START condition, the SDA and SCL pins are already sampled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF is set, the START condition is aborted, and the I2C module is reset into its IDLE state. If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete.
FIGURE 16-19:
FIRST START BIT TIMING
Write to SEN bit occurs here Set S bit (SSPSTAT<3>) SDA = 1, SCL = 1 At completion of START bit, Hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st bit TBRG TBRG S 2nd bit
TBRG SDA
SCL
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 153
PIC18FXX39
16.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING
A Repeated START condition occurs when the RSEN bit (SSPCON2<1>) is programmed high and the I2C logic module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin will be de-asserted (brought high). When SCL is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG, while SCL is high. Following this, the RSEN bit (SSPCON2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit will not be set until the baud rate generator has timed out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
16.4.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Repeated START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated START condition is complete.
FIGURE 16-20:
REPEAT START CONDITION WAVEFORM
Write to SSPCON2 occurs here. SDA = 1, SCL (no change).
Set S (SSPSTAT<3>) SDA = 1, SCL = 1 At completion of START bit, hardware clears RSEN bit and sets SSPIF TBRG 1st bit Write to SSPBUF occurs here TBRG TBRG Sr = Repeated START
TBRG SDA Falling edge of ninth clock End of Xmit SCL
TBRG
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
16.4.10 I2C MASTER MODE TRANSMISSION 16.4.10.3 ACKSTAT Status Flag
Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the buffer full flag bit, BF, and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL is held low for one baud rate generator rollover count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time, if an address match occurred, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 16-21). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will de-assert the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2<6>). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the baud rate generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is cleared when the slave has sent an Acknowledge (ACK = 0), and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data.
16.4.11
I2C MASTER MODE RECEPTION
Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: In the MSSP module, the RCEN bit must be set after the ACK sequence or the RCEN bit will be disregarded.
The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the baud rate generator is suspended from counting, holding SCL low. The MSSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>).
16.4.11.1
BF Status Flag
In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read.
16.4.11.2
SSPOV Status Flag
In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception.
16.4.11.3
WCOL Status Flag
16.4.10.1
BF Status Flag
If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
In Transmit mode, the BF bit (SSPSTAT<0>) is set when the CPU writes to SSPBUF and is cleared when all 8 bits are shifted out.
16.4.10.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 155
FIGURE 16-21:
DS30485A-page 156
Write SSPCON2<0> SEN = 1 START condition begins From slave clear ACKSTAT bit SSPCON2<6> R/W = 0 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 Transmitting Data or Second Half of 10-bit Address D0 ACK SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P A6 A5 A4 A3 A2 ACKSTAT in SSPCON2 = 1 SSPIF Cleared in software Cleared in software service routine From SSP interrupt Cleared in software BF (SSPSTAT<0>) SSPBUF written SEN After START condition, SEN cleared by hardware SSPBUF is written in software PEN
PIC18FXX39
I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Preliminary
R/W
2002 Microchip Technology Inc.
FIGURE 16-22:
2002 Microchip Technology Inc.
Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a receiver by programming SSPCON2<3>, (RCEN = 1) ACK from Slave R/W = 1 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically RCEN = 1 start next receive RCEN cleared automatically ACK ACK from Master SDA = ACKDT = 0 Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 PEN bit = 1 written here
Write to SSPCON2<0> (SEN = 1) Begin START Condition
SEN = 0 Write to SSPBUF occurs here Start XMIT
Transmit Address to Slave
SDA D0
A7 A1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1
A6 A5 A4 A3 A2
D0
ACK ACK is not sent Bus Master terminates transfer
SCL
Set SSPIF interrupt at end of receive
S
1 5 1 2 3 4 5 1 2 3 4
2
3 4 8 6 7 8 9
6
7 9
5
6
7
8
9
Set SSPIF at end of receive
P
Set SSPIF interrupt at end of Acknowledge sequence
Data shifted in on falling edge of CLK
SSPIF
Cleared in software Cleared in software
Set SSPIF interrupt at end of Acknowledge sequence Cleared in software Cleared in software
I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
Preliminary
SDA = 0, SCL = 1 while CPU responds to SSPIF
Cleared in software
Set P bit (SSPSTAT<4>) and SSPIF
BF (SSPSTAT<0>)
Last bit is shifted into SSPSR and contents are unloaded into SSPBUF
SSPOV
SSPOV is set because SSPBUF is still full
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ACKEN
DS30485A-page 157
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16.4.12 ACKNOWLEDGE SEQUENCE TIMING 16.4.13 STOP CONDITION TIMING
An Acknowledge sequence is enabled by setting the Acknowledge sequence enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG) and the SCL pin is de-asserted (pulled high). When the SCL pin is sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off and the MSSP module then goes into IDLE mode (Figure 16-23). A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the STOP sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to `0'. When the baud rate generator times out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 16-24).
16.4.13.1
WCOL Status Flag
16.4.12.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur).
If the user writes the SSPBUF when a STOP sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur).
FIGURE 16-23:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG SDA SCL D0 ACK TBRG ACKEN automatically cleared
8
9
SSPIF Cleared in software Set SSPIF at the end of Acknowledge sequence
Set SSPIF at the end of receive Note: TBRG = one baud rate generator period.
Cleared in software
FIGURE 16-24:
STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2 Set PEN SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set TBRG
Falling edge of 9th clock SCL
SDA
ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition.
Note: TBRG = one baud rate generator period.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
16.4.14 SLEEP OPERATION
I2C
16.4.17
While in SLEEP mode, the module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled).
MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION
16.4.15
EFFECT OF A RESET
A RESET disables the MSSP module and terminates the current transfer.
16.4.16
MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is IDLE, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the STOP condition occurs. In multi-master operation, the SDA line must be monitored for arbitration, to see if the signal level is the expected output level. This check is performed in hardware, with the result placed in the BCLIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A START Condition A Repeated START Condition An Acknowledge Condition
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA, by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag BCLIF and reset the I2C port to its IDLE state (Figure 16-25). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. If a START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The master will continue to monitor the SDA and SCL pins. If a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is IDLE and the S and P bits are cleared.
FIGURE 16-25:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn't match what is driven by the master. Bus collision has occurred.
SDA
SCL
Set bus collision interrupt (BCLIF)
BCLIF
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 159
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16.4.17.1 Bus Collision During a START Condition
During a START condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the START condition (Figure 16-26). SCL is sampled low before SDA is asserted low (Figure 16-27). If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 16-28). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The baud rate generator is then reloaded and counts down to `0', and during this time, if the SCL pins are sampled as '0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a START condition, is that no two bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address following the START condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated START or STOP conditions.
During a START condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the START condition is aborted, * the BCLIF flag is set, and * the MSSP module is reset to its IDLE state (Figure 16-26). The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to `0'. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition.
FIGURE 16-26:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1.
SDA
SCL Set SEN, enable START condition if SDA = 1, SCL = 1 SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SEN cleared automatically because of bus collision. SSP module reset into IDLE state.
BCLIF
SSPIF SSPIF and BCLIF are cleared in software.
DS30485A-page 160
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 16-27: BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG TBRG
SDA Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared in software S SSPIF '0' '0' '0' '0'
SCL
SEN
FIGURE 16-28:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1 Set S Less than TBRG
TBRG
Set SSPIF
SDA
SDA pulled low by other master. Reset BRG and assert SDA.
SCL
S
SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1
SEN
BCLIF
'0'
S
SSPIF SDA = 0, SCL = 1 Set SSPIF Interrupts cleared in software
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 161
PIC18FXX39
16.4.17.2 Bus Collision During a Repeated START Condition
During a Repeated START condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1'. reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated START condition, see Figure 16-30. If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated START condition is complete.
When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to `0'. The SCL pin is then de-asserted, and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data '0', Figure 16-29). If SDA is sampled high, the BRG is
FIGURE 16-29:
SDA SCL
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software '0' '0'
S SSPIF
FIGURE 16-30:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG TBRG
SDA SCL BCLIF SCL goes low before SDA, Set BCLIF. Release SDA and SCL. Interrupt cleared in software RSEN S SSPIF
'0'
DS30485A-page 162
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
16.4.17.3 Bus Collision During a STOP Condition
Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is de-asserted, SCL is sampled low before SDA goes high. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to `0'. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0' (Figure 16-31). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure 16-32).
b)
FIGURE 16-31:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
TBRG TBRG TBRG
SDA sampled low after TBRG, Set BCLIF
SDA SDA asserted low SCL PEN BCLIF P SSPIF
'0' '0'
FIGURE 16-32:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG TBRG TBRG
SDA Assert SDA SCL PEN BCLIF P SSPIF '0' '0' SCL goes low before SDA goes high, Set BCLIF
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 163
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NOTES:
DS30485A-page 164
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
17.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The USART can be configured in the following modes: * Asynchronous (full-duplex) * Synchronous - Master (half-duplex) * Synchronous - Slave (half-duplex) In order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter: * bit SPEN (RCSTA<7>) must be set (= 1), * bit TRISC<6> must be cleared (= 0), and * bit TRISC<7> must be set (= 1). Register 17-1 shows the Transmit Status and Control Register (TXSTA) and Register 17-2 shows the Receive Status and Control Register (RCSTA).
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 165
PIC18FXX39
REGISTER 17-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 CSRC bit 7 bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode.
bit 6
bit 5
bit 4
SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data Can be Address/Data bit or a parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3 bit 2
bit 1
bit 0
DS30485A-page 166
Preliminary
2002 Microchip Technology Inc.
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REGISTER 17-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 SPEN bit 7 bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data This can be Address/Data bit or a parity bit, and must be calculated by user firmware Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 167
PIC18FXX39
17.1 USART Baud Rate Generator (BRG)
Example 17-1 shows the calculation of the baud rate error for the following conditions: * * * * FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 17-1 shows the formula for computation of the baud rate for different USART modes, which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 17-1. From this, the error in baud rate can be determined.
It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
17.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
EXAMPLE 17-1:
Desired Baud Rate Solving for X: X X X Calculated Baud Rate Error
CALCULATING BAUD RATE ERROR
= FOSC / (64 (X + 1)) = ( (FOSC / Desired Baud Rate) / 64 ) - 1 = ((16000000 / 9600) / 64) - 1 = [25.042] = 25 = = = = = 16000000 / (64 (25 + 1)) 9615 (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate (9615 - 9600) / 9600 0.16%
TABLE 17-1:
SYNC
BAUD RATE FORMULA
BRGH = 0 (Low Speed) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) N/A
0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) 1 Legend: X = value in SPBRG (0 to 255)
TABLE 17-2:
Name TXSTA RCSTA SPBRG
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 -- ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on POR, BOR 0000 -010 0000 -00x 0000 0000 Value on All Other RESETS 0000 -010 0000 -00x 0000 0000
Bit 7 CSRC SPEN
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
DS30485A-page 168
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 17-3:
BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW
BAUD RATES FOR SYNCHRONOUS MODE
SPBRG value (decimal) 129 103 32 19 0 255 SPBRG value (decimal) 207 51 41 12 7 0 255 SPBRG value (decimal) 103 51 12 9 2 1 0 255 33 MHz KBAUD NA NA NA NA NA 77.10 95.93 294.64 485.30 8250 32.23 10 MHz KBAUD NA NA NA NA 19.23 75.76 96.15 312.50 500 2500 9.77 % ERROR +0.16 -1.36 +0.16 +4.17 0 % ERROR +0.39 -0.07 -1.79 -2.94 SPBRG value (decimal) 106 85 27 16 0 255 SPBRG value (decimal) 129 32 25 7 4 0 255 SPBRG value (decimal) 92 46 11 8 2 1 0 255 25 MHz KBAUD NA NA NA NA NA 77.16 96.15 297.62 480.77 6250 24.41 % ERROR +0.47 +0.16 -0.79 -3.85 SPBRG value (decimal) 80 64 20 12 0 255 SPBRG value (decimal) 185 92 22 18 5 3 0 255 SPBRG value (decimal) 207 103 25 12 2 2 0 0 255 20 MHz KBAUD NA NA NA NA NA 76.92 96.15 294.12 500 5000 19.53 % ERROR +0.16 +0.16 -1.96 0 SPBRG value (decimal) 64 51 16 9 0 255 SPBRG value (decimal) 131 65 16 12 3 2 0 255 SPBRG value (decimal) 26 6 2 0 0 255
FOSC = 40 MHz KBAUD NA NA NA NA NA 76.92 96.15 303.03 500 10000 39.06 % ERROR +0.16 +0.16 +1.01 0 -
FOSC = 16 MHz KBAUD NA NA NA NA 19.23 76.92 95.24 307.70 500 4000 15.63 % ERROR +0.16 +0.16 -0.79 +2.56 0 -
7.15909 MHz KBAUD NA NA NA 9.62 19.24 77.82 94.20 298.35 447.44 1789.80 6.99 1 MHz KBAUD NA 1.20 2.40 9.62 19.23 83.33 83.33 250 NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 +8.51 -13.19 -16.67 % ERROR +0.23 +0.23 +1.32 -1.88 -0.57 -10.51 -
5.0688 MHz KBAUD NA NA NA 9.60 19.20 74.54 97.48 316.80 422.40 1267.20 4.95 % ERROR 0 0 -2.94 +1.54 +5.60 -15.52 -
FOSC = 4 MHz KBAUD NA NA NA 9.62 19.23 76.92 1000 333.33 500 1000 3.91 % ERROR +0.16 +0.16 +0.16 +4.17 +11.11 0 -
3.579545 MHz KBAUD NA NA NA 9.62 19.04 74.57 99.43 298.30 447.44 894.89 3.50 % ERROR +0.23 -0.83 -2.90 +3.57 -0.57 -10.51 -
32.768 kHz KBAUD 0.30 1.17 2.73 8.20 NA NA NA NA NA 8.20 0.03 % ERROR +1.14 -2.48 +13.78 -14.67 -
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 169
PIC18FXX39
TABLE 17-4:
BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
SPBRG value (decimal) 64 32 7 6 1 0 0 255 SPBRG value (decimal) 207 103 25 12 2 2 0 0 255 SPBRG value (decimal) 207 51 25 6 2 0 0 255 33 MHz KBAUD NA NA 2.40 9.55 19.10 73.66 103.13 257.81 NA 515.63 2.01 10 MHz KBAUD NA 1.20 2.40 9.77 19.53 78.13 78.13 156.25 NA 156.25 0.61 % ERROR +0.16 +0.16 +1.73 +1.73 +1.73 -18.62 -47.92 % ERROR -0.07 -0.54 -0.54 -4.09 +7.42 -14.06 SPBRG value (decimal) 214 53 26 6 4 1 0 255 SPBRG value (decimal) 129 64 15 7 1 1 0 0 255 SPBRG value (decimal) 185 46 22 5 2 0 0 255 25 MHz KBAUD NA NA 2.40 9.53 19.53 78.13 97.66 NA NA 390.63 1.53 % ERROR -0.15 -0.76 +1.73 +1.73 +1.73 SPBRG value (decimal) 162 40 19 4 3 0 255 SPBRG value (decimal) 92 46 11 5 0 0 255 SPBRG value (decimal) 51 12 6 1 0 0 255 20 MHz KBAUD NA NA 2.40 9.47 19.53 78.13 104.17 312.50 NA 312.50 1.22 % ERROR +0.16 -1.36 +1.73 +1.73 +8.51 +4.17 SPBRG value (decimal) 129 32 15 3 2 0 0 255 SPBRG value (decimal) 65 32 7 3 0 0 255 SPBRG value (decimal) 1 0 255
FOSC = 40 MHz KBAUD NA NA NA 9.62 18.94 78.13 89.29 312.50 625 625 2.44 % ERROR +0.16 -1.36 +1.73 -6.99 +4.17 +25.00 -
FOSC = 16 MHz KBAUD NA 1.20 2.40 9.62 19.23 83.33 83.33 250 NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 +8.51 -13.19 -16.67 -
7.15909 MHz KBAUD NA 1.20 2.38 9.32 18.64 111.86 NA NA NA 111.86 0.44 1 MHz KBAUD 0.30 1.20 2.23 7.81 15.63 NA NA NA NA 15.63 0.06 % ERROR +0.16 +0.16 -6.99 -18.62 -18.62 % ERROR +0.23 -0.83 -2.90 -2.90 +45.65 -
5.0688 MHz KBAUD NA 1.20 2.40 9.90 19.80 79.20 NA NA NA 79.20 0.31 % ERROR 0 0 +3.13 +3.13 +3.13 -
FOSC = 4 MHz KBAUD 0.30 1.20 2.40 8.93 20.83 62.50 NA NA NA 62.50 0.24 % ERROR -0.16 +1.67 +1.67 -6.99 +8.51 -18.62 -
3.579545 MHz KBAUD 0.30 1.19 2.43 9.32 18.64 55.93 NA NA NA 55.93 0.22 % ERROR +0.23 -0.83 +1.32 -2.90 -2.90 -27.17 -
32.768 kHz KBAUD 0.26 NA NA NA NA NA NA NA NA 0.51 0.002 % ERROR -14.67 -
DS30485A-page 170
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 17-5:
BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
SPBRG value (decimal) 129 32 25 7 4 0 255 SPBRG value (decimal) 103 51 12 9 2 1 0 255 SPBRG value (decimal) 207 103 25 12 0 255 33 MHz KBAUD NA NA NA 9.60 19.28 76.39 98.21 294.64 515.63 2062.50 8,06 10 MHz KBAUD NA NA NA 9.62 18.94 78.13 89.29 312.50 625 625 2.44 % ERROR +0.16 -1.36 +1.73 -6.99 +4.17 +25.00 % ERROR -0.07 +0.39 -0.54 +2.31 -1.79 +3.13 SPBRG value (decimal) 214 106 26 20 6 3 0 255 SPBRG value (decimal) 64 32 7 6 1 0 0 255 SPBRG value (decimal) 185 92 22 11 2 1 0 0 255 25 MHz KBAUD NA NA NA 9.59 19.30 78.13 97.66 312.50 520.83 1562.50 6.10 % ERROR -0.15 +0.47 +1.73 +1.73 +4.17 +4.17 SPBRG value (decimal) 162 80 19 15 4 2 0 255 SPBRG value (decimal) 185 46 22 5 4 0 0 0 255 SPBRG value (decimal) 207 51 25 6 2 0 0 255 20 MHz KBAUD NA NA NA 9.62 19.23 78.13 96.15 312.50 416.67 1250 4.88 % ERROR +0.16 +0.16 +1.73 +0.16 +4.17 -16.67 SPBRG value (decimal) 129 64 15 12 3 2 0 255 SPBRG value (decimal) 131 32 16 3 2 0 0 255 SPBRG value (decimal) 6 1 0 0 255
FOSC = 40 MHz KBAUD NA NA NA NA 19.23 75.76 96.15 312.50 500 2500 9.77 % ERROR +0.16 -1.36 +0.16 +4.17 0 -
FOSC = 16 MHz KBAUD NA NA NA 9.62 19.23 76.92 100 333.33 500 1000 3.91 % ERROR +0.16 +0.16 +0.16 +4.17 +11.11 0 -
7.15909 MHz KBAUD NA NA 2.41 9.52 19.45 74.57 89.49 447.44 447.44 447.44 1.75 1 MHz KBAUD 0.30 1.20 2.40 8.93 20.83 62.50 NA NA NA 62.50 0.24 % ERROR +0.16 +0.16 +0.16 -6.99 +8.51 -18.62 % ERROR +0.23 -0.83 +1.32 -2.90 -6.78 +49.15 -10.51 -
5.0688 MHz KBAUD NA NA 2.40 9.60 18.64 79.20 105.60 316.80 NA 316.80 1.24 % ERROR 0 0 -2.94 +3.13 +10.00 +5.60 -
FOSC = 4 MHz KBAUD NA 1.20 2.40 9.62 19.23 NA NA NA NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 -
3.579545 MHz KBAUD NA 1.20 2.41 9.73 18.64 74.57 111.86 223.72 NA 55.93 0.22 % ERROR +0.23 +0.23 +1.32 -2.90 -2.90 +16.52 -25.43 -
32.768 kHz KBAUD 0.29 1.02 2.05 NA NA NA NA NA NA 2.05 0.008 % ERROR -2.48 -14.67 -14.67 -
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 171
PIC18FXX39
17.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data bits and one STOP bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. To set up an asynchronous transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 17.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). Note: TXIF is not cleared immediately upon loading data into the transmit buffer TXREG. The flag bit becomes valid in the second instruction cycle following the load instruction.
2. 3. 4. 5. 6. 7.
17.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 17-1. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and
FIGURE 17-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXREG Register 8 MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN *** TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK pin
TXIE
DS30485A-page 172
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 17-2:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
START bit
bit 0
bit 1 Word 1
bit 7/8
STOP bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 17-3:
Write to TXREG
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Word 1 Word 2
BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) START bit bit 0 bit 1 Word 1 bit 7/8 STOP bit START bit Word 2 bit 0
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg.
Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 17-6:
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 6 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR Value on All Other RESETS
Bit 7
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE PIR1 PIE1 IPR1 RCSTA TXREG TXSTA PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
TMR0IF INT0IF
-- -- --
0000 000x 0000 000u
TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 TMR2IP TMR1IP 0000 0000 0000 0000 OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
CREN ADDEN SYNC --
FERR BRGH
USART Transmit Register
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 173
PIC18FXX39
17.2.2 USART ASYNCHRONOUS RECEIVER 17.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
The receiver block diagram is shown in Figure 17-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 17.1). 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is required, set the BRGH bit. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 1.
FIGURE 17-4:
USART RECEIVE BLOCK DIAGRAM
CREN x64 Baud Rate CLK / 64 or / 16 MSb STOP (8) 7 RSR Register *** 1 LSb 0 START OERR FERR
SPBRG
Baud Rate Generator RX9 RC7/RX/DT Pin Buffer and Control Data Recovery RX9D RCREG Register FIFO
SPEN 8 Interrupt RCIF RCIE Data Bus
DS30485A-page 174
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 17-5:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
ASYNCHRONOUS RECEPTION
START bit bit0 bit1 bit7/8 STOP bit START bit bit0 bit7/8 STOP bit START bit bit7/8 STOP bit
Word 1 RCREG
Word 2 RCREG
TABLE 17-7:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR 0000 000x Value on All Other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 -010 0000 0000
Bit 7 GIE/GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
TMR0IF INT0IF
-- -- --
TMR2IF TMR1IF 0000 0000 TMR2IE TMR1IE 0000 0000 TMR2IP TMR1IP 0000 0000 OERR TRMT RX9D TX9D 0000 -00x 0000 0000 0000 -010 0000 0000
CREN ADDEN FERR SYNC -- BRGH
USART Receive Register Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 175
PIC18FXX39
17.3 USART Synchronous Master Mode
(PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. TRMT is a read only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. To set up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate (Section 17.1). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. Note: TXIF is not cleared immediately upon loading data into the transmit buffer TXREG. The flag bit becomes valid in the second instruction cycle following the load instruction.
In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>).
17.3.1
USART SYNCHRONOUS MASTER TRANSMISSION
The USART transmitter block diagram is shown in Figure 17-1. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE
TABLE 17-8:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF
-- -- --
Bit 1 INT0IF TMR2IF
Bit 0 RBIF TMR1IF
Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 -010 0000 0000
Value on All Other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 -010 0000 0000
GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
TMR2IE TMR1IE TMR2IP TMR1IP OERR TRMT RX9D TX9D
CREN ADDEN SYNC --
FERR BRGH
USART Transmit Register Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
DS30485A-page 176
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 17-6: SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit TRMT '1'
bit 0
bit 1 Word 1
bit 2
bit 7
bit 0
bit 1 Word 2
bit 7
Write Word1
Write Word2
TXEN bit Note:
'1'
Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
FIGURE 17-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit0 bit1 bit2 bit6 bit7
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 177
PIC18FXX39
17.3.2 USART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. 3. Initialize the SPBRG register for the appropriate baud rate (Section 17.1). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Ensure bits CREN and SREN are clear. 4. 5. 6. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
TABLE 17-9:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 TMR0IF
-- -- --
Bit 7 GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC
Bit 1 INT0IF
Bit 0 RBIF
Value on POR, BOR
Value on All Other RESETS
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP CREN SYNC
0000 000x 0000 000u
TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 TMR2IP TMR1IP 0000 0000 0000 0000 OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
FERR BRGH
USART Receive Register Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
FIGURE 17-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG Note: '0'
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
'0'
Timing diagram demonstrates Sync Master mode with bit SREN = '1' and bit BRGH = '0'.
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PIC18FXX39
17.4 USART Synchronous Slave Mode
To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>).
17.4.1
USART SYNCHRONOUS SLAVE TRANSMIT
2. 3. 4. 5. 6. 7. 8.
The operation of the Synchronous Master and Slave modes are identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector.
e)
TABLE 17-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF -- -- -- FERR BRGH Bit 1 INT0IF Bit 0 RBIF Value on POR, BOR Value on All Other RESETS
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP
0000 000x 0000 000u
TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 TMR2IP TMR1IP 0000 0000 0000 0000 OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
CREN ADDEN SYNC --
USART Transmit Register Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
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Preliminary
DS30485A-page 179
PIC18FXX39
17.4.2 USART SYNCHRONOUS SLAVE RECEPTION
To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register, and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector.
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 17-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Bit 7 GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) SPEN CSRC Bit 6 PEIE/ GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE SSPIP ADDEN -- Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR Value on All Other RESETS
TMR0IE INT0IE RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP CREN SYNC
TMR0IF INT0IF -- -- -- FERR BRGH
0000 000x 0000 000u
TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 TMR2IP TMR1IP 0000 0000 0000 0000 OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -010 0000 -010 0000 0000 0000 0000
USART Receive Register Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
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PIC18FXX39
18.0 COMPATIBLE 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The A/D module has four registers: * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1)
The Analog-to-Digital (A/D) converter module has five inputs for the PIC18F2X39 devices and eight for the PIC18F4X39 devices. This module has the ADCON0 and ADCON1 register definitions that are compatible with the mid-range A/D module. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number.
The ADCON0 register, shown in Register 18-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 18-2, configures the functions of the port pins.
REGISTER 18-1:
ADCON0 REGISTER
R/W-0 ADCS1 bit 7 R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit 0
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits (ADCON0 bits in bold)
ADCON1 0 0 0 0 1 1 1 1 ADCON0 00 01 10 11 00 01 10 11 Clock Conversion FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from the internal A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from the internal A/D RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (AN0) 001 = Channel 1 (AN1) 010 = Channel 2 (AN2) 011 = Channel 3 (AN3) 100 = Channel 4 (AN4) 101 = Channel 5 (AN5)(1) 110 = Channel 6 (AN6)(1) 111 = Channel 7 (AN7)(1) Note 1: These channels are unimplemented on PIC18F2X39 devices. Do not select any unimplemented channel.
bit 2
GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion, which is automatically cleared by hardware when the A/D conversion is complete) 0 = A/D conversion not in progress Unimplemented: Read as '0' ADON: A/D On bit 1 = A/D converter module is powered up 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 1 bit 0
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Preliminary
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PIC18FXX39
REGISTER 18-2: ADCON1 REGISTER
R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as '0'. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as '0'. ADCS2: A/D Conversion Clock Select bit (ADCON1 bits in bold) ADCON1 ADCON0
0 0 0 0 1 1 1 1 00 01 10 11 00 01 10 11
R/W-0 ADCS2
U-0 --
U-0 --
R/W-0 PCFG3
R/W-0 PCFG2
R/W-0 PCFG1
R/W-0 PCFG0 bit 0
bit 6
Clock Conversion
FOSC/2 FOSC/8 FOSC/32 FRC (clock derived from the internal A/D RC oscillator) FOSC/4 FOSC/16 FOSC/64 FRC (clock derived from the internal A/D RC oscillator)
bit 5-4 bit 3-0
Unimplemented: Read as '0' PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG <3:0> 0000 0001 0010 0011 0100 0101 011x 1000 1001 1010 1011 1100 1101 1110 1111 AN7 A A D D D D D A D D D D D D D AN6 A A D D D D D A D D D D D D D AN5 A A D D D D D A A A A D D D D AN4 A A A A D D D A A A A A D D D AN3 A VREF+ A VREF+ A VREF+ D VREF+ A VREF+ VREF+ VREF+ VREF+ D VREF+ AN2 A A A A D D D VREFA A VREFVREFVREFD VREFAN1 A A A A A A D A A A A A A D D AN0 A A A A A A D A A A A A A A A VREF+ VDD AN3 VDD AN3 VDD AN3 -- AN3 VDD AN3 AN3 AN3 AN3 VDD AN3 VREFVSS VSS VSS VSS VSS VSS -- AN2 VSS VSS AN2 AN2 AN2 VSS AN2 C/R 8/0 7/1 5/0 4/1 3/0 2/1 0/0 6/2 6/0 5/1 4/2 3/2 2/2 1/0 1/2
A = Analog input D = Digital I/O C/R = # of analog input channels / # of A/D voltage references Legend: R = Readable bit - n = Value at POR Note: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
On any device RESET, the port pins that are multiplexed with analog functions (ANx) are forced to be an analog input.
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PIC18FXX39
The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/ VREF+ pin and RA2/AN2/VREF- pin. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference) or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ ADRESL registers, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit, ADIF is set. The block diagram of the A/D module is shown in Figure 18-1.
FIGURE 18-1:
A/D BLOCK DIAGRAM
CHS<2:0>
111 110 101 100 VAIN (Input Voltage) 10-bit Converter A/D PCFG<3:0> VDD VREF+ Reference Voltage VREFVSS * These channels are implemented only on the PIC18F4X39 devices. 011 010 001 000
AN7* AN6* AN5* AN4 AN3 AN2 AN1 AN0
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Preliminary
DS30485A-page 183
PIC18FXX39
The value that is in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 18.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit * Set PEIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (interrupts disabled) OR 6. 7. * Waiting for the A/D interrupt Read A/D Result registers (ADRESH/ADRESL); clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
18.1
A/D Acquisition Requirements
2.
3. 4.
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 18-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. Note: When the conversion is started, the holding capacitor is disconnected from the input pin.
FIGURE 18-2:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS
Rs
ANx
VAIN
CPIN 5 pF VT = 0.6V
I LEAKAGE 500 nA
CHOLD = 120 pF
VSS
Legend: CPIN = input capacitance VT = threshold voltage I LEAKAGE = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
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Preliminary
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PIC18FXX39
To calculate the minimum acquisition time, Equation 18-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.
EQUATION 18-1:
TACQ = =
ACQUISITION TIME
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF
EQUATION 18-2:
VHOLD = or = TC
A/D MINIMUM CHARGING TIME
(VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) -(120 pF)(1 k + RSS + RS) ln(1/2048)
Example 18-1 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: * * * * * * CHOLD Rs Conversion Error VDD Temperature VHOLD = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0
EXAMPLE 18-1:
TACQ = TACQ = TC =
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF 2 s + TC + [(Temp - 25C)(0.05 s/C)] -CHOLD (RIC + RSS + RS) ln(1/2048) -120 pF (1 k + 7 k + 2.5 k) ln(0.0004883) -120 pF (10.5 k) ln(0.0004883) -1.26 s (-7.6246) 9.61 s 2 s + 9.61 s + [(50C - 25C)(0.05 s/C)] 11.61 s + 1.25 s 12.86 s
Temperature coefficient is only required for temperatures > 25C.
TACQ =
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Preliminary
DS30485A-page 185
PIC18FXX39
18.2 Selecting the A/D Conversion Clock 18.3 Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. The seven possible options for TAD are: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal A/D module RC oscillator (2-6 s) The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins, that are desired as analog inputs, must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins) may cause the input buffer to consume current that is out of the device's specification.
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 18-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 18-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Maximum Device Frequency PIC18FXX39 1.25 MHz 2.50 MHz 5.00 MHz 10.00 MHz 20.00 MHz 40.00 MHz -- PIC18LFXX39 666 kHz 1.33 MHz 2.67 MHz 5.33 MHz 10.67 MHz 21.33 MHz --
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC
ADCS2:ADCS0 000 100 001 101 010 110 011
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PIC18FXX39
18.4 A/D Conversions
Figure 18-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait is required before the next acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
FIGURE 18-3:
A/D CONVERSION TAD CYCLES
b8 b7 b6 b5 b4 b3 b2 b1 b0 b0
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9
Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
18.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification. Figure 18-4 shows the operation of the A/D result justification. The extra bits are loaded with `0's. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.
FIGURE 18-4:
A/D RESULT JUSTIFICATION
10-bit Result ADFM = 1 ADFM = 0
7 0000 00
2107
0
7
0765 0000 00
0
ADRESH
ADRESL 10-bit Result
ADRESH 10-bit Result
ADRESL
Right Justified
Left Justified
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Preliminary
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PIC18FXX39
TABLE 18-2:
Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 PORTA TRISA PORTE LATE TRISE Bit 7 GIE/ GIEH PSPIF(1) PSPIE(1) PSPIP(1) -- -- --
SUMMARY OF A/D REGISTERS
Bit 6 PEIE/ GIEL ADIF ADIE ADIP -- -- -- Bit 5 TMR0IE RCIF RCIE RCIP -- -- -- Bit 4 INT0IE TXIF TXIE TXIP EEIF EEIE EEIP Bit 3 RBIE SSPIF SSPIE SSPIP BCLIF BCLIE BCLIP Bit 2 TMR0IF -- -- -- LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP -- -- -- Value on POR, BOR Value on All Other RESETS
0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---1 1111 ---1 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
A/D Result Register A/D Result Register ADCS1 ADFM -- -- -- -- IBF ADCS0 ADCS2 RA6 -- -- OBF CHS2 -- RA5 -- -- IBOV CHS1 -- RA4 -- -- PSPMODE CHS0 PCFG3 RA3 -- -- -- GO/DONE PCFG2 RA2 RE2 LATE2 -- PCFG1 RA1 RE1 LATE1 ADON PCFG0 RA0 RE0 LATE0
0000 00-0 0000 00-0 ---- -000 ---- -000 --0x 0000 --0u 0000 --11 1111 --11 1111 ---- -000 ---- -000 ---- -xxx ---- -uuu 0000 -111 0000 -111
PORTA Data Direction Register
PORTE Data Direction bits
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X39 devices; always maintain these bits clear.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
19.0 LOW VOLTAGE DETECT
In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks" before the device voltage exits the valid operating range. This can be done using the Low Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower then the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be "turned off" by the software, which minimizes the current consumption for the device. Figure 19-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shutdown the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference TB - TA is the total time for shutdown.
FIGURE 19-1:
TYPICAL LOW VOLTAGE DETECT APPLICATION
Voltage
VA VB Legend: VA = LVD trip point VB = Minimum valid device operating voltage TA TB
Time
The block diagram for the LVD module is shown in Figure 19-2. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the
supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2V internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 19-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
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PIC18FXX39
FIGURE 19-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM
VDD LVDIN LVD Control Register
16 to 1 MUX
- +
LVDIF
LVDEN
Internally Generated Reference Voltage 1.2V Typical
The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to `1111'. In this state, the comparator input is multiplexed from the external input pin,
LVDIN (Figure 19-3). This gives users flexibility, because it allows them to configure the Low Voltage Detect interrupt to occur at any voltage in the valid operating range.
FIGURE 19-3:
LOW VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM
VDD VDD LVD Control Register LVDIN 16 to 1 MUX LVDEN
- +
Externally Generated Trip Point
LVD
VxEN BODEN
EN BGAP
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PIC18FXX39
19.1 Control Register
The Low Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry.
REGISTER 19-1:
LVDCON REGISTER
U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3 R/W-1 LVDL2 R/W-0 LVDL1 R/W-1 LVDL0 bit 0
bit 7-6 bit 5
Unimplemented: Read as '0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit LVDL3:LVDL0: Low Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V - 4.77V 1101 = 4.2V - 4.45V 1100 = 4.0V - 4.24V 1011 = 3.8V - 4.03V 1010 = 3.6V - 3.82V 1001 = 3.5V - 3.71V 1000 = 3.3V - 3.50V 0111 = 3.0V - 3.18V 0110 = 2.8V - 2.97V 0101 = 2.7V - 2.86V 0100 = 2.5V - 2.65V 0011 = 2.4V - 2.54V 0010 = 2.2V - 2.33V 0001 = 2.0V - 2.12V 0000 = Reserved Note: LVDL3:LVDL0 modes, which result in a trip point below the valid operating voltage of the device, are not tested.
bit 4
bit 3-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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19.2 Operation
Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. The following steps are needed to set up the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD Trip Point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits).
2. 3. 4. 5.
6.
Figure 19-4 shows typical waveforms that the LVD module may be used to detect.
FIGURE 19-4:
CASE 1: VDD
LOW VOLTAGE DETECT WAVEFORMS
LVDIF may not be set
VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software
CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST
LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists
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19.2.1 REFERENCE VOLTAGE SET POINT
19.3
Operation During SLEEP
The Internal Reference Voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36. The low voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 19-4.
When enabled, the LVD circuitry continues to operate during SLEEP. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from SLEEP. Device execution will continue from the interrupt vector address if interrupts have been globally enabled.
19.4
Effects of a RESET
A device RESET forces all registers to their RESET state. This forces the LVD module to be turned off.
19.2.2
CURRENT CONSUMPTION
When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B.
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NOTES:
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20.0 SPECIAL FEATURES OF THE CPU
20.1 Configuration Bits
The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h - 3FFFFFh), which can only be accessed using Table Reads and Table Writes. Programming the configuration registers is done in a manner similar to programming the FLASH memory (see Section 5.5.1). The only difference is the configuration registers are written a byte at a time. The sequence of events for programming configuration registers is: 1. Load table pointer with address of configuration register being written. 2. Write a single byte using the TBLWT instruction. 3. Set EEPGD to point to program memory, set the CFGS bit to access configuration registers, and set WREN to enable byte writes. 4. Disable interrupts. 5. Write 55h to EECON2. 6. Write AAh to EECON2. 7. Set the WR bit. This will begin the write cycle. 8. CPU will stall for duration of write (approximately 2 ms using internal timer). 9. Execute a NOP. 10. Re-enable interrupts.
There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving Operating modes and offer code protection. These are: * OSC Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code Protection * ID Locations * In-Circuit Serial Programming All PIC18FXX39 devices have a Watchdog Timer, which is permanently enabled via the configuration bits, or software controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options.
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TABLE 20-1:
File Name 300001h 300002h 300003h 300005h 300006h 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh 3FFFFEh 3FFFFFh CONFIG1H CONFIG2L CONFIG2H CONFIG3H CONFIG4L CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H DEVID1 DEVID2
CONFIGURATION BITS AND DEVICE IDS
Bit 7 -- -- -- -- DEBUG -- CPD -- WRTD -- -- DEV2 DEV10 Bit 6 -- -- -- -- -- -- CPB -- WRTB -- EBTRB DEV1 DEV9 Bit 5 --(1) -- -- -- -- -- -- -- WRTC -- -- DEV0 DEV8 Bit 4 -- -- -- -- -- -- -- -- -- -- -- REV4 DEV7 Bit 3 -- BORV1 WDTPS2 -- -- --(1) -- --(1) -- --(1) -- REV3 DEV6 Bit 2 FOSC2 BORV0 WDTPS1 -- LVP CP2 -- WRT2 -- EBTR2 -- REV2 DEV5 Bit 1 FOSC1 BOREN WDTPS0 -- -- CP1 -- WRT1 -- EBTR1 -- REV1 DEV4 Bit 0 FOSC0 PWRTEN WDTEN --(1) STVREN CP0 -- WRT0 -- EBTR0 -- REV0 DEV3 Default/ Unprogrammed Value
--1- -010 ---- 1111 ---- 1111 ---- ---1 1--- -1-1 ---- 1111 11-- ------- 1111 111- ------- 1111 -1-- ---(2)
0000 0100
Legend: x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as `0'. Note 1: Unimplemented, but reserved; maintain this bit set. 2: See Register 20-11 for DEVID1 values.
REGISTER 20-1:
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
U-0 -- bit 7 U-0 -- U-1 -- U-0 -- U-0 -- R/P-0 FOSC2 R/P-1 FOSC1 R/P-0 FOSC0 bit 0
bit 7-6 bit 5 bit 4-3 bit 2-0
Unimplemented: Read as `0' Unimplemented and reserved: Maintain as `1' Unimplemented: Read as `0' FOSC2:FOSC0: Oscillator Selection bits 111 = Reserved 110 = HS oscillator with PLL enabled; clock frequency = (4 x FOSC) 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as divide-by-4 clock output 011 = Reserved 010 = HS oscillator 001 = Reserved 000 = Reserved Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
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REGISTER 20-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 -- bit 7 bit 7-4 bit 3-2 Unimplemented: Read as `0' BORV1:BORV0: Brown-out Reset Voltage bits 11 = VBOR set to 2.5V 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V BOREN: Brown-out Reset Enable bit 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 BORV1 R/P-1 BORV0 R/P-1 BOREN R/P-1 PWRTEN bit 0
bit 1
bit 0
REGISTER 20-3:
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDTEN bit 0
bit 7-4 bit 3-1
Unimplemented: Read as `0' WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
bit 0
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REGISTER 20-4: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-1 DEBUG bit 7 bit 7 U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 LVP U-0 -- R/P-1 STVREN bit 0
DEBUG: Background Debugger Enable bit 1 = Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins. 0 = Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug. Unimplemented: Read as `0' LVP: Low Voltage ICSP Enable bit 1 = Low Voltage ICSP enabled 0 = Low Voltage ICSP disabled Unimplemented: Read as `0' STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack Full/Underflow will cause RESET 0 = Stack Full/Underflow will not cause RESET Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
bit 6-3 bit 2
bit 1 bit 0
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REGISTER 20-5: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0 -- bit 7 bit 7-4 bit 3 bit 2 Unimplemented: Read as `0' Unimplemented and reserved: Maintain as `1' CP2: Code Protection bit(1) 1 = Block 2 (004000-005FFFh) not code protected 0 = Block 2 (004000-005FFFh) code protected CP1: Code Protection bit 1 = Block 1 (002000-003FFFh) not code protected 0 = Block 1 (002000-003FFFh) code protected CP0: Code Protection bit 1 = Block 0 (000200-001FFFh) not code protected 0 = Block 0 (000200-001FFFh) code protected Note 1: Unimplemented in PIC18FX439 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-1 -- R/C-1 CP2(1) R/C-1 CP1 R/C-1 CP0 bit 0
bit 1
bit 0
REGISTER 20-6:
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1 CPD bit 7 R/C-1 CPB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code protected 0 = Data EEPROM code protected CPB: Boot Block Code Protection bit 1 = Boot block (000000-0001FFh) not code protected 0 = Boot block (000000-0001FFh) code protected Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
bit 6
bit 5-0
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REGISTER 20-7: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0 -- bit 7 bit 7-4 bit 3 bit 2 Unimplemented: Read as `0' Unimplemented and reserved: Maintain as `1' WRT2: Write Protection bit(1) 1 = Block 2 (004000-005FFFh) not write protected 0 = Block 2 (004000-005FFFh) write protected WRT1: Write Protection bit 1 = Block 1 (002000-003FFFh) not write protected 0 = Block 1 (002000-003FFFh) write protected WRT0: Write Protection bit 1 = Block 0 (000200h-001FFFh) not write protected 0 = Block 0 (000200h-001FFFh) write protected Note 1: Unimplemented in PIC18FX439 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-1 -- R/C-1 WRT2(1) R/C-1 WRT1 R/C-1 WRT0 bit 0
bit 1
bit 0
REGISTER 20-8:
CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/C-1 WRTD bit 7 R/C-1 WRTB C-1 WRTC U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write protected 0 = Data EEPROM write protected WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0001FFh) not write protected 0 = Boot block (000000-0001FFh) write protected WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write protected 0 = Configuration registers (300000-3000FFh) write protected Note: This bit is read only, and cannot be changed in User mode. Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed
bit 6
bit 5
bit 4-0
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REGISTER 20-9: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0 -- bit 7 bit 7-4 bit 3 bit 2 Unimplemented: Read as `0' Unimplemented and reserved: Maintain as `1' EBTR2: Table Read Protection bit(1) 1 = Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks 0 = Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks EBTR1: Table Read Protection bit 1 = Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks 0 = Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks EBTR0: Table Read Protection bit 1 = Block 0 (000200h-001FFFh) not protected from Table Reads executed in other blocks 0 = Block 0 (000200h-001FFFh) protected from Table Reads executed in other blocks Note 1: Unimplemented in PIC18FX439 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-1 -- R/C-1 EBTR2(1) R/C-1 EBTR1 R/C-1 EBTR0 bit 0
bit 1
bit 0
REGISTER 20-10: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0001FFh) not protected from Table Reads executed in other blocks 0 = Boot block (000000-0001FFh) protected from Table Reads executed in other blocks Unimplemented: Read as `0' Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R/C-1 EBTRB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 5-0
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REGISTER 20-11: DEVID1: DEVICE ID REGISTER 1 FOR PIC18FXX39 (BYTE ADDRESS 3FFFFEh)
R DEV2 bit 7 bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F2539 001 = PIC18F4539 100 = PIC18F2439 101 = PIC18F4439 REV4:REV0: Revision ID bits These bits are used to indicate the device revision. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0
bit 4-0
REGISTER 20-12: DEVID2: DEVICE ID REGISTER 2 FOR PIC18FXX39 (BYTE ADDRESS 3FFFFFh)
R DEV10 bit 7 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R DEV9 R DEV8 R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 bit 0
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20.2 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the RCON register will be cleared upon a WDT time-out. The Watchdog Timer is enabled/disabled by a device configuration bit. If the WDT is enabled, software execution may not disable this function. When the WDTEN configuration bit is cleared, the SWDTEN bit enables/ disables the operation of the WDT. The WDT time-out period values may be found in the Electrical Specifications (Section 23.0) under parameter D031. Values for the WDT postscaler may be assigned using the configuration bits. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT and prevent it from timing out and generating a device RESET condition. 2: When a CLRWDT instruction is executed and the postscaler is assigned to the WDT, the postscaler count will be cleared, but the postscaler assignment is not changed.
20.2.1
CONTROL REGISTER
Register 20-13 shows the WDTCON register. This is a readable and writable register, which contains a control bit that allows software to override the WDT enable configuration bit, only when the configuration bit has disabled the WDT.
REGISTER 20-13: WDTCON REGISTER
U-0 -- bit 7 bit 7-1 bit 0 Unimplemented: Read as '0' SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = 0 Legend: R = Readable bit U = Unimplemented bit, read as `0' W = Writable bit - n = Value at POR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN bit 0
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20.2.2 WDT POSTSCALER
The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming, by the value written to the CONFIG2H configuration register.
FIGURE 20-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Postscaler 8 8 - to - 1 MUX WDTPS2:WDTPS0
WDTEN Configuration bit
SWDTEN bit
WDT Time-out Note: WDPS2:WDPS0 are bits in register CONFIG2H.
TABLE 20-2:
Name CONFIG2H RCON WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 -- IPEN -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 -- RI -- Bit 3 WDTPS2 TO -- Bit 2 WDTPS2 PD -- Bit 1 WDTPS0 POR -- Bit 0 WDTEN BOR SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer.
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20.3 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared, but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or hi-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should be considered. The MCLR pin must be at a logic high level (VIHMC). External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and will cause a "wake-up". The TO and PD bits in the RCON register can be used to determine the cause of the device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared, if a WDT time-out occurred (and caused wake-up). When the SLEEP instruction is being executed, the next instruction (PC + 2) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
20.3.1
WAKE-UP FROM SLEEP
20.3.2
WAKE-UP USING INTERRUPTS
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a Peripheral Interrupt.
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
The following peripheral interrupts can wake the device from SLEEP: PSP read or write. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. TMR3 interrupt. Timer3 must be operating as an asynchronous counter. 4. CCP Capture mode interrupt. 5. Special event trigger (Timer1 in Asynchronous mode using an external clock). 6. MSSP (START/STOP) bit detect interrupt. 7. MSSP transmit or receive in Slave mode (SPI/I2C). 8. USART RX or TX (Synchronous Slave mode). 9. A/D conversion (when A/D clock source is RC). 10. EEPROM write operation complete. 11. LVD interrupt. Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. 1. 2.
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FIGURE 20-2:
OSC1 CLKO(4) INT pin INTF Flag (INTCON<1>) GIEH bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Fetched Inst(PC) = SLEEP Instruction Inst(PC - 1) Executed PC+2 Inst(PC + 2) SLEEP PC+4 PC+4 Inst(PC + 4) Inst(PC + 2) Dummy Cycle PC + 4 0008h Inst(0008h) Dummy Cycle 000Ah Inst(000Ah) Inst(0008h) Processor in SLEEP Interrupt Latency(3) TOST(2)
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Note
1: 2: 3: 4:
XT, HS or LP Oscillator mode assumed. GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. TOST = 1024 TOSC (drawing not to scale). This delay will not occur for RC and EC Osc modes. CLKO is not available in these Osc modes, but shown here for timing reference.
20.4
Program Verification and Code Protection
The overall structure of the code protection on the PIC18 FLASH devices differs significantly from other PICmicro devices. The user program memory is divided on binary boundaries into individual blocks, each of which has three separate code protection bits associated with it: * Code Protect bit (CPn) * Write Protect bit (WRTn) * External Block Table Read bit (EBTRn) The code protection bits are located in Configuration Registers 5L through 7H. Their locations within the registers are summarized in Table 20-3. In the PIC18FXX39 family, program memory is divided into segments of 8 Kbytes. The first block in turn divided into a boot block of 512 bytes and a separately protected remainder (Block 0) of 7.5 Kbytes. This means for PIC18FXX39 devices, that there may be up to five blocks, depending on the program memory size. The organization of the blocks and their associated code protection bits are shown in Figure 20-3.
For PIC18FX439 devices, program memory is divided into three blocks: a boot block, Block 0 (7.5 Kbytes) and Block 1 (8 Kbytes). Block 1 is further divided in half; the upper portion above 3000h is reserved, and unavailable to user applications. The entire block can be protected as a whole by bits CP1, WRT1 and EBTR1. By default, Block 1 is not code protected. For PIC18FX539 devices, program memory is divided into five blocks: the boot block, Block 0 (7.5 Kbytes), and Blocks 1 through 3 (8 Kbytes). Code protection is implemented for the boot block and Blocks 0 through 2. There is no provision for code protection for Block 3. Note: The reserved segments of the program memory space are used by the Motor Control kernel. For the kernel to function properly, this area must not be write protected. If users are developing applications that require code protection for PIC18FX439 devices, they should restrict program code (or at least those sections requiring protection) to below the 1FFFh memory boundary.
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FIGURE 20-3: CODE PROTECTED PROGRAM MEMORY FOR PIC18FXX39
MEMORY SIZE/DEVICE 16 Kbytes (PIC18FX439) Boot Block 32 Kbytes (PIC18FX539) Boot Block Address Range 000000h 0001FFh 000200h Block 0 Block 0 001FFFh Block 1 Block 1 Reserved 003000h 003FFFh 004000h Unimplemented Read `0's Block 2 005FFFh 006000h Unimplemented Read `0's Reserved 007FFFh 008000h -- CP2, WRT2, EBTR2 002000h 002FFFh CP1, WRT1, EBTR1 CP0, WRT0, EBTR0 Block Code Protection Controlled By:
CPB, WRTB, EBTRB
Unimplemented Read `0's
Unimplemented Read `0's
(Unimplemented Memory Space)
1FFFFFh
TABLE 20-3:
SUMMARY OF CODE PROTECTION REGISTERS
Bit 7 -- CPD -- WRTD -- -- Bit 6 -- CPB -- WRTB -- EBTRB Bit 5 -- -- -- WRTC -- -- Bit 4 -- -- -- -- -- -- Bit 3 --(1) -- --(1) -- --(1) -- Bit 2 CP2 -- WRT2 -- EBTR2 -- Bit 1 CP1 -- WRT1 -- EBTR1 -- Bit 0 CP0 -- WRT0 -- EBTR0 --
File Name 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H
Legend: Shaded cells are unimplemented. Note 1: Unimplemented, but reserved; maintain this bit set.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 207
PIC18FXX39
20.4.1 PROGRAM MEMORY CODE PROTECTION
The user memory may be read to, or written from, any location using the Table Read and Table Write instructions. The device ID may be read with Table Reads. The configuration registers may be read and written with the Table Read and Table Write instructions. In User mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from Table Writes if the WRTn configuration bit is `0'. The EBTRn bits control Table Reads. For a block of user memory with the EBTRn bit set to `0', a Table Read instruction that executes from within that block is allowed to read. A Table Read instruction that executes from a location outside of that block is not allowed to read, and will result in reading `0's. Figures 20-4 through 20-6 illustrate Table Write and Table Read protection. Note: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a block erase function. The block erase function can only be initiated via ICSP or an external programmer.
FIGURE 20-4:
TABLE WRITE (WRTn) DISALLOWED
Program Memory 000000h 0001FFh 000200h WRTB,EBTRB = 11 Configuration Bit Settings
Register Values
TBLPTR = 000FFF PC = 001FFE 001FFFh 002000h
WRT0,EBTR0 = 01 TBLWT *
WRT1,EBTR1 = 11 003FFFh 004000h PC = 004FFE TBLWT * 005FFFh WRT2,EBTR2 = 11
Results: All Table Writes disabled to Blockn whenever WRTn = 0.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 20-5: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED
Program Memory 000000h 0001FFh 000200h TBLPTR = 000FFF WRTB,EBTRB = 11 Configuration Bit Settings Register Values
WRT0,EBTR0 = 10 001FFFh 002000h TBLRD * 003FFFh 004000h 005FFFh
PC = 002FFE
WRT1,EBTR1 = 11
WRT2,EBTR2 = 11
Results: All Table Reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of `0'.
FIGURE 20-6:
EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED
Program Memory 000000h 0001FFh 000200h Configuration Bit Settings WRTB,EBTRB = 11
Register Values
TBLPTR = 000FFF PC = 001FFE TBLRD * 001FFFh 002000h
WRT0,EBTR0 = 10
WRT1,EBTR1 = 11 003FFFh 004000h WRT2,EBTR2 = 11 005FFFh Results: Table Reads permitted within Blockn, even when EBTRBn = 0. TABLAT register returns the value of the data at the location TBLPTR.
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Preliminary
DS30485A-page 209
PIC18FXX39
20.4.2 DATA EEPROM CODE PROTECTION
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies.
The entire Data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of Data EEPROM. WRTD inhibits external writes to Data EEPROM. The CPU can continue to read and write Data EEPROM, regardless of the protection bit settings.
20.8
Low Voltage ICSP Programming
20.4.3
CONFIGURATION REGISTER PROTECTION
The configuration registers can be write protected. The WRTC bit controls protection of the configuration registers. In User mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer.
20.5
ID Locations
Eight memory locations (200000h - 200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are accessible during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code protected. The sequence for programming the ID locations is similar to programming the FLASH memory (see Section 5.5.1).
The LVP bit configuration register CONFIG4L enables low voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB5/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. During programming, VDD is applied to the MCLR/VPP pin. To enter Programming mode, VDD must be applied to the RB5/PGM, provided the LVP bit is set. The LVP bit defaults to a `1' from the factory. Note 1: The High Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in low voltage ICSP mode, the RB5 pin can no longer be used as a general purpose I/O pin, and should be held low during normal operation to protect against inadvertent ICSP mode entry. 3: When using low voltage ICSP programming (LVP), the pull-up on RB5 becomes disabled. If TRISB bit 5 is cleared, thereby setting RB5 as an output, LATB bit 5 must also be cleared for proper operation. If Low Voltage Programming mode is not used, the LVP bit can be programmed to a '0' and RB5/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on MCLR/VPP. It should be noted that once the LVP bit is programmed to `0', only the High Voltage Programming mode is available and only High Voltage Programming mode can be used to program the device. When using low voltage ICSP, the part must be supplied 4.5V to 5.5V, if a bulk erase will be executed. This includes reprogramming of the code protect bits from an on-state to an off-state. For all other cases of low voltage ICSP, the part may be programmed at the normal operating voltage. This means unique user IDs, or user code can be reprogrammed or added.
20.6
In-Circuit Serial Programming
PIC18FXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware, or a custom firmware to be programmed.
20.7
In-Circuit Debugger
When the DEBUG bit in configuration register CONFIG4L is programmed to a '0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 20-4 shows which features are consumed by the background debugger.
TABLE 20-4:
I/O pins Stack
DEBUGGER RESOURCES
RB6, RB7 2 levels 512 bytes 10 bytes
Program Memory Data Memory
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PIC18FXX39
21.0 INSTRUCTION SET SUMMARY
The PIC18FXXX instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16-bits), but there are three instructions that require two program memory locations. Each single word instruction is a 16-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the Call or Return instructions (specified by `s') * The mode of the Table Read and Table Write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for three double-word instructions. These three instructions were made double-word instructions, so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 21-1 shows the general formats that the instructions can have. All examples use the format `nnh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 21-2, lists the instructions recognized by the Microchip Assembler (MPASMTM). Section 21.1 provides a description of each instruction.
The PIC18FXXX instruction set summary in Table 21-2 lists byte-oriented, bit-oriented, literal and control operations. Table 21-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a')
The file register designator 'f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a')
The bit field designator 'b' selects the number of the bit affected by the operation, while the file register designator 'f' represents the number of the file in which the bit is located.
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Preliminary
DS30485A-page 211
PIC18FXX39
TABLE 21-1:
Field a
OPCODE FIELD DESCRIPTIONS
Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register. Used to select the current RAM bank. Destination select bit d = 0: store result in WREG, d = 1: store result in file register f. Destination, either the WREG register or the specified register file location. 8-bit Register file address (0x00 to 0xFF). 12-bit Register file address (0x000 to 0xFFF). This is the source address. 12-bit Register file address (0x000 to 0xFFF). This is the destination address. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). Label name. The mode of the TBLPTR register for the Table Read and Table Write instructions. Only used with Table Read and Table Write instructions: No Change to register (such as TBLPTR with Table Reads and Writes). Post-Increment register (such as TBLPTR with Table Reads and Writes). Post-Decrement register (such as TBLPTR with Table Reads and Writes). Pre-Increment register (such as TBLPTR with Table Reads and Writes). The relative address (2's complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions. Product of Multiply high byte. Product of Multiply low byte. Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) Unused or Unchanged. Working register (accumulator). Don't care (0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 21-bit Table Pointer (points to a Program Memory location). 8-bit Table Latch. Top-of-Stack. Program Counter. Program Counter Low Byte. Program Counter High Byte. Program Counter High Byte Latch. Program Counter Upper Byte Latch. Global Interrupt Enable bit. Watchdog Timer. Time-out bit. Power-down bit.
bbb BSR d
dest f fs fd k label mm * *+ *+* n PRODH PRODL s
u WREG x
TBLPTR TABLAT TOS PC PCL PCH PCLATH PCLATU GIE WDT TO PD [ ( <> italics ] )
C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative. Optional. Contents. Assigned to. Register bit field. In the set of. User defined term (font is courier).
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PIC18FXX39
FIGURE 21-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 15 10 9 87 OPCODE d a 0 f (FILE #) ADDWF MYREG, W, B Example Instruction
d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 f (Destination FILE #) 0 f (Source FILE #) 0 MOVFF MYREG1, MYREG2
f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B OPCODE b (BIT #) a
b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 12 11 n<19:8> (literal) 87 n<7:0> (literal) 0 0 GOTO Label 8 7 k (literal) 0 MOVLW 0x7F
n = 20-bit immediate value 15 OPCODE 15 12 11 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 11 10 n<10:0> (literal) 87 n<7:0> (literal) 0 BC MYFUNC 0 BRA MYFUNC 87 S n<7:0> (literal) 0 0 CALL MYFUNC
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Preliminary
DS30485A-page 213
PIC18FXX39
TABLE 21-2:
Mnemonic, Operands
PIC18FXXX INSTRUCTION SET
Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF BCF BSF BTFSC BTFSS BTG f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, b, a f, b, a f, b, a f, b, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 1 1 1 (2 or 3) 1 (2 or 3) 1 0010 01da0 0010 0da 0001 01da 0110 101a 0001 11da 0110 001a 0110 010a 0110 000a 0000 01da 0010 11da 0100 11da 0010 10da 0011 11da 0100 10da 0001 00da 0101 00da 1100 ffff 1111 ffff 0110 111a 0000 001a 0110 110a 0011 01da 0100 01da 0011 00da 0100 00da 0110 100a 0101 01da 0101 0101 0011 0110 0001 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1
1, 2 1, 2
1, 2
ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N ffff None ffff None ffff Z, N ffff ffff ffff ffff ffff None None None None None
1, 2 4 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff 1, 2 1, 2 3, 4 3, 4 1, 2
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 21-2:
Mnemonic, Operands CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP n n n n n n n n n n, s -- -- n -- -- -- -- n s k s -- Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device RESET Return from interrupt enable Return with literal in WREG Return from Subroutine Go into Standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None TO, PD C None
PIC18FXXX INSTRUCTION SET (CONTINUED)
Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes
None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD
4
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.
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Preliminary
DS30485A-page 215
PIC18FXX39
TABLE 21-2:
Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG Table Read Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 1 1 1 2 1 1 1 2 1 1 2 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None
PIC18FXXX INSTRUCTION SET (CONTINUED)
Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes
DATA MEMORY PROGRAM MEMORY OPERATIONS 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111
2 (5)
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.
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Preliminary
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PIC18FXX39
21.1
ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Instruction Set
ADD literal to W [ label ] ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z
0000 1111 kkkk kkkk
ADDWF k Syntax: Operands:
ADD W to f [ label ] ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z
0010 01da ffff ffff
f [,d [,a]
Operation: Status Affected: Encoding: Description:
The contents of W are added to the 8-bit literal 'k' and the result is placed in W. 1 1 Q2
Read literal 'k' ADDLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x15
Q4
Write to W
Add W to register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR is used. 1 1 Q2
Read register 'f' ADDWF
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W W = =
Before Instruction
0x10 0x25
Q3
Process Data REG, 0, 0
Q4
Write to destination
After Instruction Example:
W REG W REG = = = =
Before Instruction
0x17 0xC2 0xD9 0xC2
After Instruction
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 217
PIC18FXX39
ADDWFC Syntax: Operands: ADD W and Carry bit to f [ label ] ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N,OV, C, DC, Z
0010 00da ffff ffff
ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
AND literal with W [ label ] ANDLW 0 k 255 (W) .AND. k W N,Z
0000 1011 kkkk kkkk
f [,d [,a]
k
Operation: Status Affected: Encoding: Description:
Add W, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed in data memory location 'f'. If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden. 1 1
The contents of W are ANDed with the 8-bit literal 'k'. The result is placed in W. 1 1 Q2
Read literal 'k' ANDLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x5F
Q4
Write to W
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q2
Read register 'f' ADDWFC 1 0x02 0x4D 0 0x02 0x50
Q3
Process Data REG, 0, 1
Q4
Write to destination
Before Instruction
W W = = 0xA3 0x03
After Instruction
Example:
Carry bit = REG = W =
Before Instruction
After Instruction
Carry bit = REG = W =
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Preliminary
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PIC18FXX39
ANDWF Syntax: Operands: AND W with f [ label ] ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N,Z
0001 01da ffff ffff
BC f [,d [,a] Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Carry [ label ] BC n -128 n 127 if carry bit is `1' (PC) + 2 + 2n PC None
1110 0010 nnnn nnnn
Operation: Status Affected: Encoding: Description:
The contents of W are AND'ed with register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden (default). 1 1 Q2
Read register 'f' ANDWF
If the Carry bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: Q1
Decode
Words: Cycles: Q3
Process Data REG, 0, 0
Q4
Write to destination
Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
W REG W REG = = = =
Before Instruction
0x17 0xC2 0x02 0xC2
If No Jump: Q1
Decode
Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BC 5
Q4
No operation
After Instruction
Example:
PC
Before Instruction
address (HERE) 1; address (HERE+12) 0; address (HERE+2)
After Instruction
If Carry PC If Carry PC
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 219
PIC18FXX39
BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 255 0b7 a [0,1] 0 f None
1001 bbba ffff ffff
BN f,b[,a] Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Negative [ label ] BN n -128 n 127 if negative bit is `1' (PC) + 2 + 2n PC None
1110 0110 nnnn nnnn
Operation: Status Affected: Encoding: Description:
Bit 'b' in register 'f' is cleared. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' BCF
Words: Cycles: Q Cycle Activity: Q1
Decode
If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q3
Process Data FLAG_REG,
Q4
Write register 'f' 7, 0
Q Cycle Activity: If Jump: Q1
Decode
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
Before Instruction
FLAG_REG = 0xC7
No operation
After Instruction
FLAG_REG = 0x47
If No Jump: Q1
Decode
Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BN Jump
Q4
No operation
Example:
PC
Before Instruction
address (HERE) 1; address (Jump) 0; address (HERE+2)
After Instruction
If Negative PC If Negative PC
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PIC18FXX39
BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry [ label ] BNC -128 n 127 if carry bit is `0' (PC) + 2 + 2n PC None
1110 0011 nnnn nnnn
BNN Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Negative [ label ] BNN -128 n 127 if negative bit is `0' (PC) + 2 + 2n PC None
1110 0111 nnnn nnnn
n
n
If the Carry bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Negative bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
If No Jump: Q1
Decode
Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BNC Jump
Q4
No operation
If No Jump: Q1
Decode
Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BNN Jump
Q4
No operation
Example:
PC
Example:
PC
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE+2)
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE+2)
After Instruction
If Carry PC If Carry PC
After Instruction
If Negative PC If Negative PC
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Preliminary
DS30485A-page 221
PIC18FXX39
BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow [ label ] BNOV -128 n 127 if overflow bit is `0' (PC) + 2 + 2n PC None
1110 0101 nnnn nnnn
BNZ Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Zero [ label ] BNZ -128 n 127 if zero bit is `0' (PC) + 2 + 2n PC None
1110 0001 nnnn nnnn
n
n
If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
If No Jump: Q1
Decode
Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE+2)
Q4
No operation
If No Jump: Q1
Decode
Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BNZ Jump
Q4
No operation
Example:
PC
Example:
PC
Before Instruction After Instruction
If Overflow PC If Overflow PC
Before Instruction
address (HERE) 0; address (Jump) 1; address (HERE+2)
After Instruction
If Zero PC If Zero PC
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PIC18FXX39
BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] BRA n -1024 n 1023 (PC) + 2 + 2n PC None
1101 0nnn nnnn nnnn
BSF Syntax: Operands:
Bit Set f [ label ] BSF 0 f 255 0b7 a [0,1] 1 f None
1000 bbba ffff ffff
f,b[,a]
Operation: Status Affected: Encoding: Description:
Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2
Read literal 'n' No operation
Words: Cycles: Q Cycle Activity: Q1
Decode No operation
Bit 'b' in register 'f' is set. If `a' is 0 Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2
Read register 'f' BSF = =
Words: Cycles: Q3
Process Data No operation
Q4
Write to PC No operation
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write register 'f'
Example: Example:
PC HERE = = BRA Jump
FLAG_REG, 7, 1 0x0A 0x8A
Before Instruction
FLAG_REG
Before Instruction
address (HERE) address (Jump)
After Instruction
FLAG_REG
After Instruction
PC
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Preliminary
DS30485A-page 223
PIC18FXX39
BTFSC Syntax: Operands: Bit Test File, Skip if Clear [ label ] BTFSC f,b[,a] 0 f 255 0b7 a [0,1] skip if (f) = 0 None
1011 bbba ffff ffff
BTFSS Syntax: Operands:
Bit Test File, Skip if Set [ label ] BTFSS f,b[,a] 0 f 255 0b7 a [0,1] skip if (f) = 1 None
1010 bbba ffff ffff
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
If bit 'b' in register 'f' is 0, then the next instruction is skipped. If bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a twocycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
If bit 'b' in register 'f' is 1, then the next instruction is skipped. If bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3
Process Data
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q Cycle Activity: Q1
Decode
Q2
Read register 'f'
Q4
No operation
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSC : :
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSS : :
Q4
No operation No operation
Example:
FLAG, 1, 0
Example:
FLAG, 1, 0
Before Instruction
PC address (HERE) 0; address (TRUE) 1; address (FALSE)
Before Instruction
PC address (HERE) 0; address (FALSE) 1; address (TRUE)
After Instruction
If FLAG<1> PC If FLAG<1> PC
After Instruction
If FLAG<1> PC If FLAG<1> PC
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
BTG Syntax: Operands: Bit Toggle f [ label ] BTG f,b[,a] 0 f 255 0b7 a [0,1] (f) f None
0111 bbba ffff ffff
BOV Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Overflow [ label ] BOV -128 n 127 if overflow bit is `1' (PC) + 2 + 2n PC None
1110 0100 nnnn nnnn
n
Operation: Status Affected: Encoding: Description:
Bit 'b' in data memory location 'f' is inverted. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' BTG = =
Words: Cycles: Q Cycle Activity: Q1
Decode
If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q3
Process Data PORTC, 4, 0 No operation
Q4
Write register 'f'
Q Cycle Activity: If Jump: Q1
Decode
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Example:
PORTC PORTC
Before Instruction:
0111 0101 [0x75] 0110 0101 [0x65]
After Instruction:
If No Jump: Q1
Decode
Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BOV Jump
Q4
No operation
Example:
PC
Before Instruction
address (HERE) 1; address (Jump) 0; address (HERE+2)
After Instruction
If Overflow PC If Overflow PC
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Preliminary
DS30485A-page 225
PIC18FXX39
BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero [ label ] BZ n -128 n 127 if Zero bit is `1' (PC) + 2 + 2n PC None
1110 0000 nnnn nnnn
CALL Syntax: Operands: Operation:
Subroutine Call [ label ] CALL k [,s] 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (STATUS) STATUSS, (BSR) BSRS None
1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8
If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2)
Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1
Decode No operation
Q2
Read literal 'n' No operation
Q3
Process Data No operation
Q4
Write to PC No operation
Subroutine call of entire 2 Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If 's' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2
Read literal 'k'<7:0>, No operation HERE =
If No Jump: Q1
Decode
Words: Q2
Read literal 'n' HERE = = = = =
Q3
Process Data BZ Jump
Q4
No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Push PC to stack No operation CALL
Q4
Read literal 'k'<19:8>, Write to PC No operation
Example:
PC
Before Instruction
address (HERE) 1; address (Jump) 0; address (HERE+2)
After Instruction
If Zero PC If Zero PC
No operation
Example:
PC
THERE,1
Before Instruction
address (HERE) address (THERE) address (HERE + 4) W BSR STATUS
After Instruction
PC = TOS = WS = BSRS = STATUSS=
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f [ label ] CLRF 0 f 255 a [0,1] 000h f 1Z Z
0110 101a ffff ffff
CLRWDT f [,a] Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD
0000 0000 0000 0100
Status Affected: Encoding: Description:
Clears the contents of the specified register. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' CLRF = =
CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. 1 1 Q2
No operation CLRWDT = = = = = ? 0x00 0 1 1
Words: Cycles: Q Cycle Activity: Q1
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q3
Process Data FLAG_REG,1 0x5A 0x00
Q4
Write register 'f'
Decode
Example: Example: Before Instruction
FLAG_REG
Before Instruction
WDT Counter
After Instruction
WDT Counter WDT Postscaler TO PD
After Instruction
FLAG_REG
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 227
PIC18FXX39
COMF Syntax: Operands: Complement f [ label ] COMF 0 f 255 d [0,1] a [0,1] ( f ) dest N, Z
0001 11da ffff ffff
CPFSEQ f [,d [,a] Syntax: Operands: Operation:
Compare f with W, skip if f = W [ label ] CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None
0110 001a ffff ffff
f [,a]
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The contents of register 'f' are complemented. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' COMF = = = 0x13 0x13 0xEC
Words: Cycles: Q Cycle Activity: Q1
Decode
Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If 'f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
Q3
Process Data REG, 0, 0
Q4
Write to destination
Words: Cycles:
Example:
REG REG W
Before Instruction After Instruction
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NEQUAL EQUAL = = = = = = No operation No operation
Q4
No operation No operation
Example:
CPFSEQ REG, 0 : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL)
Before Instruction
PC Address W REG
After Instruction
If REG PC If REG PC
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Preliminary
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PIC18FXX39
CPFSGT Syntax: Operands: Operation: Compare f with W, skip if f > W [ label ] CPFSGT 0 f 255 a [0,1] (f) - (W), skip if (f) > (W) (unsigned comparison) None
0110 010a ffff ffff
CPFSLT Syntax: Operands: Operation:
Compare f with W, skip if f < W [ label ] CPFSLT 0 f 255 a [0,1] (f) - (W), skip if (f) < (W) (unsigned comparison) None
0110 000a ffff ffff
f [,a]
f [,a]
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Compares the contents of data memory location 'f' to the contents of the W by performing an unsigned subtraction. If the contents of 'f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If the contents of 'f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is 0, the Access Bank will be selected. If `a' is 1, the BSR will not be overridden (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NGREATER GREATER = = > = = No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NLESS LESS = = < = = No operation No operation
Q4
No operation No operation
Q4
No operation No operation
Example:
Example:
CPFSGT REG, 0 : :
CPFSLT REG, 1 : : Address (HERE) ? W; Address (LESS) W; Address (NLESS)
Before Instruction
PC W
Before Instruction
PC W Address (HERE) ? W; Address (GREATER) W; Address (NGREATER)
After Instruction
If REG PC If REG PC
After Instruction
If REG PC If REG PC
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 229
PIC18FXX39
DAW Syntax: Operands: Operation: Decimal Adjust W Register [ label ] DAW None If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 W<7:4>; else (W<7:4>) W<7:4>; Status Affected: Encoding: Description: C
0000 0000 0000 0111
DECF Syntax: Operands:
Decrement f [ label ] DECF f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z
0000 01da ffff ffff
Operation: Status Affected: Encoding: Description:
DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Q2
Read register W DAW
Decrement register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' DECF = = = = 0x01 0 0x00 1
Words: Cycles: Q Cycle Activity: Q1
Decode
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data CNT, 1, 0
Q4
Write to destination
Q3
Process Data
Q4
Write W
Example:
CNT Z CNT Z
Example1:
W C DC W C DC = = = = = =
Before Instruction After Instruction
Before Instruction
0xA5 0 0 0x05 1 0
After Instruction
Example 2:
Before Instruction
W C DC W C DC = = = = = = 0xCE 0 0 0x34 1 0
After Instruction
DS30485A-page 230
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
DECFSZ Syntax: Operands: Decrement f, skip if 0 [ label ] DECFSZ f [,d [,a]] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None
0010 11da ffff ffff
DCFSNZ Syntax: Operands:
Decrement f, skip if not 0 [ label ] DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None
0100 11da ffff ffff
f [,d [,a]
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register 'f' are decremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
The contents of register 'f' are decremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a twocycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE CONTINUE No operation No operation DECFSZ GOTO
Q4
No operation No operation CNT, 1, 1 LOOP
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE ZERO NZERO = = = = = No operation No operation DCFSNZ : : ?
Q4
No operation No operation
Example:
Example:
TEMP, 1, 0
Before Instruction
PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE+2)
Before Instruction
TEMP
After Instruction
After Instruction
TEMP If TEMP PC If TEMP PC TEMP - 1, 0; Address (ZERO) 0; Address (NZERO)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 231
PIC18FXX39
GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch [ label ] GOTO k 0 k 1048575 k PC<20:1> None
1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8
INCF Syntax: Operands:
Increment f [ label ] INCF f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z
0010 10da ffff ffff
Operation: Status Affected: Encoding: Description:
GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2 Q2
Read literal 'k'<7:0>, No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' INCF = = = = = = = = 0xFF 0 ? ? 0x00 1 1 1
Q3
No operation No operation
Q4
Read literal 'k'<19:8>, Write to PC No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data CNT, 1, 0
Q4
Write to destination
No operation
Example:
PC =
GOTO THERE Address (THERE)
Example:
CNT Z C DC CNT Z C DC
After Instruction
Before Instruction
After Instruction
DS30485A-page 232
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
INCFSZ Syntax: Operands: Increment f, skip if 0 [ label ] INCFSZ f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None
0011 11da ffff ffff
INFSNZ Syntax: Operands:
Increment f, skip if not 0 [ label ] INFSNZ f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None
0100 10da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f'. (default) If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
The contents of register 'f' are incremented. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a twocycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
If skip: Q1
No operation
If skip: Q2
No operation
Q3
No operation
Q4
No operation
Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NZERO ZERO = = = = = No operation No operation INCFSZ : :
Q4
No operation No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE ZERO NZERO = = No operation No operation INFSNZ
Q4
No operation No operation
Example:
CNT, 1, 0
Example:
REG, 1, 0
Before Instruction
PC CNT If CNT PC If CNT PC Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO)
Before Instruction
PC REG If REG PC If REG PC Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)
After Instruction
After Instruction
= = =
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 233
PIC18FXX39
IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR literal with W [ label ] IORLW k 0 k 255 (W) .OR. k W N, Z
0000 1001 kkkk kkkk
IORWF Syntax: Operands:
Inclusive OR W with f [ label ] IORWF f [,d [,a] 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z
0001 00da ffff ffff
Operation: Status Affected: Encoding: Description:
The contents of W are OR'ed with the eight-bit literal 'k'. The result is placed in W. 1 1 Q2
Read literal 'k' IORLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x35
Q4
Write to W
Inclusive OR W with register 'f'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' IORWF 0x13 0x91 0x13 0x93
Words: Example:
W W = =
Cycles: Q Cycle Activity: Q1
Decode
Before Instruction
0x9A 0xBF
Q3
Process Data RESULT, 0, 1
Q4
Write to destination
After Instruction
Example:
RESULT = W =
Before Instruction
After Instruction
RESULT = W =
DS30485A-page 234
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Load FSR [ label ] LFSR f,k 0f2 0 k 4095 k FSRf None
1110 1111 1110 0000 00ff k7kkk k11kkk kkkk
MOVF Syntax: Operands:
Move f [ label ] MOVF f [,d [,a] 0 f 255 d [0,1] a [0,1] f dest N, Z
0101 00da ffff ffff
Operation: Status Affected: Encoding: Description:
The 12-bit literal 'k' is loaded into the file select register pointed to by 'f'. 2 2 Q2
Read literal 'k' MSB
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write literal 'k' MSB to FSRfH Write literal 'k' to FSRfL
The contents of register 'f' are moved to a destination dependent upon the status of `d'. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). Location 'f' can be anywhere in the 256 byte bank. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' MOVF = = = =
Decode
Read literal 'k' LSB
Process Data
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
FSR2H FSR2L
LFSR 2, 0x3AB = = 0x03 0xAB
After Instruction
Q3
Process Data REG, 0, 0 0x22 0xFF 0x22 0x22
Q4
Write W
Example:
REG W
Before Instruction
After Instruction
REG W
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 235
PIC18FXX39
MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f [ label ] MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None
1100 1111 ffff ffff ffff ffff ffffs ffffd
MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Move literal to low nibble in BSR [ label ] k BSR None
0000 0001 kkkk kkkk
MOVLB k
0 k 255
The 8-bit literal 'k' is loaded into the Bank Select Register (BSR). 1 1 Q2
Read literal 'k'
The contents of source register 'fs' are moved to destination register 'fd'. Location of source 'fs' can be anywhere in the 4096 byte data space (000h to FFFh), and location of destination 'fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Note: The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled. See Section 8.0 for more information.
Q3
Process Data
Q4
Write literal 'k' to BSR
Example:
MOVLB = =
5 0x02 0x05
Before Instruction
BSR register
After Instruction
BSR register
Words: Cycles: Q Cycle Activity: Q1
Decode
2 2 (3) Q2
Read register 'f' (src) No operation No dummy read
Q3
Process Data No operation
Q4
No operation Write register 'f' (dest)
Decode
Example:
REG1 REG2
MOVFF = = = =
REG1, REG2 0x33 0x11 0x33, 0x33
Before Instruction After Instruction
REG1 REG2
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Move literal to W [ label ] kW None
0000 1110 kkkk kkkk
MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move W to f [ label ] MOVWF f [,a] 0 f 255 a [0,1] (W) f None
0110 111a ffff ffff
MOVLW k
0 k 255
The eight-bit literal 'k' is loaded into W. 1 1 Q2
Read literal 'k' MOVLW
Q3
Process Data 0x5A
Q4
Write to W
Move data from W to register 'f'. Location 'f' can be anywhere in the 256 byte bank. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' MOVWF
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W =
After Instruction
0x5A
Q3
Process Data REG, 0
Q4
Write register 'f'
Example:
W REG W REG = = = =
Before Instruction
0x4F 0xFF 0x4F 0x4F
After Instruction
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 237
PIC18FXX39
MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with W [ label ] MULLW k 0 k 255 (W) x k PRODH:PRODL None
0000 1101 kkkk kkkk
MULWF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Multiply W with f [ label ] MULWF f [,a] 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None
0000 001a ffff ffff
An unsigned multiplication is carried out between the contents of W and the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. 1 1 Q2
Read literal 'k'
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write registers PRODH: PRODL
An unsigned multiplication is carried out between the contents of W and the register file location 'f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and 'f' are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f'
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
W PRODH PRODL
MULLW
0xC4
Q3
Process Data
Q4
Write registers PRODH: PRODL
Before Instruction
= = = = = = 0xE2 ? ? 0xE2 0xAD 0x08
After Instruction
W PRODH PRODL
Example:
W REG PRODH PRODL
MULWF
REG, 1
Before Instruction
= = = = = = = = 0xC4 0xB5 ? ? 0xC4 0xB5 0x8A 0x94
After Instruction
W REG PRODH PRODL
DS30485A-page 238
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f [ label ] NEGF f [,a] 0 f 255 a [0,1] (f)+1f N, OV, C, DC, Z
0110 110a ffff ffff
NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
No Operation [ label ] None No operation None
0000 1111 0000 xxxx 0000 xxxx 0000 xxxx
NOP
Location `f' is negated using two's complement. The result is placed in the data memory location 'f'. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value. 1 1 Q2
Read register 'f' NEGF = =
No operation. 1 1 Q2
No operation
Q3
No operation
Q4
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example: Q3
Process Data REG, 1
Q4
Write register 'f'
None.
Example:
REG REG
Before Instruction
0011 1010 [0x3A] 1100 0110 [0xC6]
After Instruction
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 239
PIC18FXX39
POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack [ label ] None (TOS) bit bucket None
0000 0000 0000 0110
PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description:
Push Top of Return Stack [ label ] None (PC+2) TOS None
0000 0000 0000 0101
POP
PUSH
The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q2
No operation POP GOTO
The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows to implement a software stack by modifying TOS, and then push it onto the return stack. 1 1 Q2
PUSH PC+2 onto return stack PUSH = = 00345Ah 000124h
Words: Cycles: Q Cycle Activity: Q1
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
No operation
Q4
No operation
Q3
POP TOS value
Q4
No operation
Decode
Example: Example:
NEW = = 0031A2h 014332h TOS PC
Before Instruction
Before Instruction
TOS Stack (1 level down)
After Instruction
PC TOS Stack (1 level down) = = = 000126h 000126h 00345Ah
After Instruction
TOS PC = = 014332h NEW
DS30485A-page 240
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call [ label ] RCALL -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None
1101 1nnn nnnn nnnn
RESET n Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1
Decode
Reset [ label ] None Reset all registers and flags that are affected by a MCLR Reset. All
0000 0000 1111 1111
RESET
Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2
Read literal 'n' Push PC to stack
This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2
Start reset RESET Reset Value Reset Value
Q3
No operation
Q4
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
Registers = Flags* =
After Instruction Q3
Process Data
Q4
Write to PC
No operation
No operation HERE
No operation RCALL Jump
No operation
Example:
PC = PC = TOS =
Before Instruction
Address (HERE) Address (Jump) Address (HERE+2)
After Instruction
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 241
PIC18FXX39
RETFIE Syntax: Operands: Operation: Return from Interrupt [ label ] s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged. GIE/GIEH, PEIE/GIEL.
0000 0000 0001 000s
RETLW Syntax: Operands: Operation:
Return Literal to W [ label ] RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None
0000 1100 kkkk kkkk
RETFIE [s]
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from Interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2
No operation
W is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q2
Read literal 'k' No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data No operation
Q4
pop PC from stack, Write to W No operation
No operation
Words: Cycles: Q Cycle Activity: Q1
Decode
Example:
CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; W contains table offset value W now has table value
Q3
No operation
Q4
pop PC from stack Set GIEH or GIEL
No operation
No operation RETFIE 1
No operation
No operation
W = offset Begin table
Example: After Interrupt
End of table
PC W BSR STATUS GIE/GIEH, PEIE/GIEL
= = = = =
TOS WS BSRS STATUSS 1
Before Instruction
W W = = 0x07 value of kn
After Instruction
DS30485A-page 242
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
RETURN Syntax: Operands: Operation: Return from Subroutine [ label ] s [0,1] (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None
0000 0000 0001 001s
RLCF Syntax: Operands:
Rotate Left f through Carry [ label ] RLCF f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) C, (C) dest<0> C, N, Z
0011 01da ffff ffff
RETURN [s]
Operation:
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs (default). 1 2 Q2
No operation No operation
The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' = 1, then the bank will be selected as per the BSR value (default). C
register f
Words: Cycles: Q Cycle Activity: Q1
Decode No operation
Words: Q3
Process Data No operation
1 1 Q2
Read register 'f' RLCF = = = = =
Q4
pop PC from stack No operation
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to destination
Example: Example: After Interrupt
PC = TOS RETURN REG C REG W C
REG, 0, 0
Before Instruction
1110 0110 0 1110 0110 1100 1100 1
After Instruction
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 243
PIC18FXX39
RLNCF Syntax: Operands: Rotate Left f (no carry) [ label ] RLNCF f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) dest<0> N, Z
0100 01da ffff ffff
RRCF Syntax: Operands:
Rotate Right f through Carry [ label ] RRCF f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) C, (C) dest<7> C, N, Z
0011 00da ffff ffff
Operation: Status Affected: Encoding: Description:
Operation:
Status Affected: Encoding: Description:
The contents of register 'f' are rotated one bit to the left. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default).
register f
The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). C
register f
Words: Cycles: Q Cycle Activity: Q1
Decode
1 1 Q2
Read register 'f' RLNCF = =
Words: Q3
Process Data
1 1 Q2
Read register 'f' RRCF = = = = =
Q4
Write to destination
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG, 0, 0
Q4
Write to destination
Example:
REG REG
REG, 1, 0
Before Instruction
1010 1011 0101 0111
Example:
REG C REG W C
After Instruction
Before Instruction
1110 0110 0 1110 0110 0111 0011 0
After Instruction
DS30485A-page 244
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
RRNCF Syntax: Operands: Rotate Right f (no carry) [ label ] RRNCF f [,d [,a] 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) dest<7> N, Z
0100 00da ffff ffff
SETF Syntax: Operands: Operation: Status Affected: Encoding: Description:
Set f [ label ] SETF 0 f 255 a [0,1] FFh f None
0110 100a ffff ffff
f [,a]
Operation: Status Affected: Encoding: Description:
The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default).
register f
The contents of the specified register are set to FFh. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' SETF = = 0x5A 0xFF
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG,1
Q4
Write register 'f'
Words: Cycles: Q Cycle Activity: Q1
Decode
1 1 Q2
Read register 'f' RRNCF = =
Example: Q3
Process Data REG, 1, 0
Before Instruction Q4
Write to destination REG
After Instruction
REG
Example 1:
REG REG
Before Instruction
1101 0111 1110 1011 RRNCF REG, 0, 0
After Instruction
Example 2:
W REG W REG = = = =
Before Instruction
? 1101 0111 1110 1011 1101 0111
After Instruction
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 245
PIC18FXX39
SLEEP Syntax: Operands: Operation: Enter SLEEP mode [ label ] SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD
0000 0000 0000 0011
SUBFWB Syntax: Operands:
Subtract f from W with borrow [ label ] SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z
0101 01da ffff ffff
f [,d [,a]
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1 Q2
No operation SLEEP
Words: Cycles: Q Cycle Activity: Q1
Decode
Subtract register 'f' and carry flag (borrow) from W (2's complement method). If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' SUBFWB = = = = = = = = 3 2 1 FF 2 0 0 1 ; result is negative SUBFWB = = = = = = = = 2 5 1 2 3 1 0 0 REG, 0, 0
Words: Q3
Process Data
Q4
Go to sleep
Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG, 1, 0
Q4
Write to destination
Example:
TO = PD = TO = PD = ? ?
Before Instruction
Example 1:
REG W C REG W C Z N
Before Instruction
After Instruction
1 0
After Instruction
If WDT causes wake-up, this bit is cleared.
Example 2:
REG W C REG W C Z N
Before Instruction
After Instruction
; result is positive REG, 1, 0
Example 3:
REG W C REG W C Z N = = = = = = = =
SUBFWB 1 2 0 0 2 1 1 0
Before Instruction
After Instruction
; result is zero
DS30485A-page 246
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
SUBLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Subtract W from literal [ label ] SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z
0000 1000 kkkk kkkk
SUBWF Syntax: Operands:
Subtract W from f [ label ] SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z
0101 11da ffff ffff
f [,d [,a]
Operation: Status Affected: Encoding: Description:
W is subtracted from the eight-bit literal 'k'. The result is placed in W. 1 1 Q2
Read literal 'k' SUBLW
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data 0x02
Q4
Write to W
Subtract W from register 'f' (2's complement method). If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' SUBWF = = = = = = = = 3 2 ? 1 2 1 0 0 SUBWF = = = = = = = = 2 2 ? 2 0 1 1 0 SUBWF = = = = = = = = 1 2 ? FFh ;(2's complement) 2 0 ; result is negative 0 1
Example 1:
W C W C Z N = = = = = =
Words: Cycles: Q Cycle Activity: Q1
Decode
Before Instruction
1 ? 1 1 0 0 SUBLW
After Instruction
; result is positive
Q3
Process Data REG, 1, 0
Q4
Write to destination
Example 1:
0x02 REG W C REG W C Z N
Example 2:
W C W C Z N = = = = = =
Before Instruction
Before Instruction
2 ? 0 1 1 0 SUBLW
After Instruction
; result is zero
After Instruction
; result is positive
Example 3:
W C W C Z N = = = = = =
0x02
Example 2:
REG W C REG W C Z N
REG, 0, 0
Before Instruction
3 ? FF ; (2's complement) 0 ; result is negative 0 1
Before Instruction
After Instruction
After Instruction
; result is zero
Example 3:
REG W C REG W C Z N
REG, 1, 0
Before Instruction
After Instruction
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 247
PIC18FXX39
SUBWFB Syntax: Operands: Subtract W from f with Borrow [ label ] SUBWFB 0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z
0101 10da ffff ffff
SWAPF Syntax: Operands:
Swap f [ label ] SWAPF f [,d [,a] 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None
0011 10da ffff ffff
f [,d [,a]
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Subtract W and the carry flag (borrow) from register 'f' (2's complement method). If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' SUBWFB = = = = = = = = 0x19 0x0D 1 0x0C 0x0D 1 0 0
Words: Cycles: Q Cycle Activity: Q1
Decode
The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in W. If 'd' is 1, the result is placed in register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' SWAPF = = 0x53 0x35
Words: Cycles: Q3
Process Data REG, 1, 0
Q4
Write to destination
Q Cycle Activity: Q1
Decode
Q3
Process Data REG, 1, 0
Q4
Write to destination
Example 1:
REG W C REG W C Z N
Before Instruction
(0001 1001) (0000 1101)
Example:
REG REG
Before Instruction After Instruction
After Instruction
(0000 1011) (0000 1101) ; result is positive
Example 2:
REG W C REG W C Z N = = = = = = = =
SUBWFB REG, 0, 0 0x1B 0x1A 0 0x1B 0x00 1 1 0 SUBWFB = = = = = = = = 0x03 0x0E 1 0xF5 0x0E 0 0 1
Before Instruction
(0001 1011) (0001 1010)
After Instruction
(0001 1011) ; result is zero REG, 1, 0
Example 3:
REG W C REG W C Z N
Before Instruction
(0000 0011) (0000 1101)
After Instruction
(1111 0100) ; [2's comp] (0000 1101) ; result is negative
DS30485A-page 248
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TBLRD Syntax: Operands: Operation: Table Read [ label ] None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) +1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) -1 TBLPTR; if TBLRD +*, (TBLPTR) +1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT;
0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +*
TBLRD Example1:
Table Read (cont'd)
TBLRD *+ ; = = = = = TBLRD +* ; = = = = = = 0xAA 0x01A357 0x12 0x34 0x34 0x01A358 0x55 0x00A356 0x34 0x34 0x00A357
TBLRD ( *; *+; *-; +*)
Before Instruction
TABLAT TBLPTR MEMORY(0x00A356)
After Instruction
TABLAT TBLPTR
Example2:
Before Instruction
TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358)
Status Affected:None Encoding:
After Instruction
TABLAT TBLPTR
Description:
This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q2
No operation No operation (Read Program Memory)
Words: Cycles:
Q Cycle Activity: Q1
Decode No operation
Q3
No operation
Q4
No operation
No No operation operation (Write TABLAT)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 249
PIC18FXX39
TBLWT Syntax: Operands: Operation: Table Write [ label ] None if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) +1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) -1 TBLPTR; if TBLWT+*, (TBLPTR) +1 TBLPTR; (TABLAT) Holding Register;
0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +*
TBLWT Example1:
Table Write (Continued)
TBLWT *+; = = = = = = +*; = = = = = = = = 0x34 0x01389A 0xFF 0xFF 0x34 0x01389B 0xFF 0x34 0x55 0x00A356 0xFF 0x55 0x00A357 0x55
TBLWT ( *; *+; *-; +*)
Before Instruction
TABLAT TBLPTR HOLDING REGISTER (0x00A356) TABLAT TBLPTR HOLDING REGISTER (0x00A356)
After Instructions (table write completion)
Example 2:
TBLWT
Before Instruction
TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B)
Status Affected: None Encoding:
After Instruction (table write completion)
Description:
This instruction uses the 3 LSbs of the TBLPTR to determine which of the 8 holding registers the TABLAT data is written to. The 8 holding registers are used to program the contents of Program Memory (P.M.). See Section 5.0 for information on writing to FLASH memory. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q3
No operation No operation
Words: Cycles:
Q Cycle Activity: Q1 Q2
Decode No operation No operation No operation (Read TABLAT)
Q4
No operation No operation (Write to Holding Register or Memory)
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, skip if 0 [ label ] TSTFSZ f [,a] 0 f 255 a [0,1] skip if f = 0 None
0110 011a ffff ffff
XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k W N, Z
0000 1010 kkkk kkkk
If 'f' = 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed, making this a twocycle instruction. If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2
Read register 'f'
The contents of W are XORed with the 8-bit literal 'k'. The result is placed in W. 1 1 Q2
Read literal 'k'
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
Write to W
Words: Cycles:
Example:
W W = =
XORLW 0xAF
0xB5 0x1A
Before Instruction After Instruction
Q Cycle Activity: Q1
Decode
Q3
Process Data
Q4
No operation
If skip: Q1
No operation
Q2
No operation
Q3
No operation
Q4
No operation
If skip and followed by 2-word instruction: Q1 Q2 Q3
No operation No operation No operation No operation HERE NZERO ZERO No operation No operation TSTFSZ : :
Q4
No operation No operation
Example:
CNT, 1
Before Instruction
PC = Address (HERE)
After Instruction
If CNT PC If CNT PC = = = 0x00, Address (ZERO) 0x00, Address (NZERO)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 251
PIC18FXX39
XORWF Syntax: Operands: Exclusive OR W with f [ label ] XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z
0001 10da ffff ffff
f [,d [,a]
Operation: Status Affected: Encoding: Description:
Exclusive OR the contents of W with register 'f'. If 'd' is 0, the result is stored in W. If 'd' is 1, the result is stored back in the register 'f' (default). If `a' is 0, the Access Bank will be selected, overriding the BSR value. If `a' is 1, then the bank will be selected as per the BSR value (default). 1 1 Q2
Read register 'f' XORWF = = = = 0xAF 0xB5 0x1A 0xB5
Words: Cycles: Q Cycle Activity: Q1
Decode
Q3
Process Data REG, 1, 0
Q4
Write to destination
Example:
REG W REG W
Before Instruction
After Instruction
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
22.0 DEVELOPMENT SUPPORT
The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files - absolute listing file - machine code The ability to use MPLAB IDE with multiple debugging tools allows users to easily switch from the costeffective simulator to a full-featured emulator with minimal retraining. The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board
22.2
MPASM Assembler
The MPASM assembler is a full-featured universal macro assembler for all PICmicro MCU's. The MPASM assembler has a command line interface and a Windows shell. It can be used as a stand-alone application on a Windows 3.x or greater system, or it can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file that contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects. * User-defined macros to streamline assembly code. * Conditional assembly for multi-purpose source files. * Directives that allow complete control over the assembly process.
22.1
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor * A project manager * Customizable toolbar and key mapping * A status bar * On-line help
22.3
MPLAB C17 and MPLAB C18 C Compilers
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 253
PIC18FXX39
22.4 MPLINK Object Linker/ MPLIB Object Librarian 22.6 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * Integration with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * Allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * Easier linking because single libraries can be included instead of many smaller files. * Helps keep code maintainable by grouping related modules together. * Allows libraries to be created and modules to be added, listed, replaced, deleted or extracted.
The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows environment were chosen to best make these features available to you, the end user.
22.7
ICEPIC In-Circuit Emulator
22.5
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multiproject software development tool.
The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
22.8 MPLAB ICD In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in realtime.
22.11 PICDEM 1 Low Cost PICmicro Demonstration Board
The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB.
22.9
PRO MATE II Universal Device Programmer
The PRO MATE II universal device programmer is a full-featured programmer, capable of operating in stand-alone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code protection in this mode.
22.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board
The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad.
22.10 PICSTART Plus Entry Level Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 255
PIC18FXX39
22.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is a LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
22.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware.
22.15 KEELOQ Evaluation and Programming Tools
KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters.
DS30485A-page 256
Preliminary
2002 Microchip Technology Inc.
24CXX/ 25CXX/ 93CXX
PIC14000
HCSXXX
PIC16C5X
PIC16C6X
PIC16C7X
PIC17C4X
PIC16F62X
PIC16C8X/ PIC16F8X
PIC16C7XX
PIC16F8XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
PIC18FXXX
MCRFXXX
MCP2510
TABLE 22-1:
MPLAB(R) Integrated Development Environment
MPLAB(R) C17 C Compiler
Software Tools
MPLAB(R) C18 C Compiler
MPASMTM Assembler/ MPLINKTM Object Linker
Programmers Debugger Emulators
Demo Boards and Eval Kits
2002 Microchip Technology Inc. ** * * ** **

MPLAB(R) ICE In-Circuit Emulator
ICEPICTM In-Circuit Emulator
MPLAB(R) ICD In-Circuit Debugger
PICSTART(R) Plus Entry Level Development Programmer
PRO MATE(R) II Universal Device Programmer
DEVELOPMENT TOOLS FROM MICROCHIP
Preliminary
PICDEMTM 1 Demonstration Board
PICDEMTM 2 Demonstration Board
PICDEMTM 3 Demonstration Board
PICDEMTM 14A Demonstration Board
PICDEMTM 17 Demonstration Board
KEELOQ(R) Evaluation Kit
KEELOQ(R) Transponder Kit
microIDTM Programmer's Kit
125 kHz microIDTM Developer's Kit
125 kHz Anticollision microIDTM Developer's Kit
13.56 MHz Anticollision microIDTM Developer's Kit
PIC18FXX39
DS30485A-page 257
MCP2510 CAN Developer's Kit
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. Development tool is available on select devices.
PIC18FXX39
NOTES:
DS30485A-page 258
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
23.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings () Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined) ...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined)..............................................200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined)..................................................................200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined).............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latchup. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. 3: PORTD and PORTE not available on the PIC18F2X39 devices.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 259
PIC18FXX39
FIGURE 23-1: PIC18FXX39 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V PIC18FXX39 4.2V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
Voltage
40 MHz
Frequency
FIGURE 23-2:
PIC18LFXX39 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V PIC18LFXX39 4.2V
Voltage
4 MHz
40 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application.
DS30485A-page 260
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
23.1 DC Characteristics: PIC18FXX39 (Industrial, Extended) PIC18LFXX39 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC18LFXX39 (Industrial) PIC18FXX39 (Industrial, Extended) Param Symbol No. VDD D001 D001 D002 D003 VDR VPOR Characteristic Supply Voltage PIC18LFXX39 PIC18FXX39 RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal PIC18LFXX39 BORV1:BORV0 = 11 BORV1:BORV0 = 10 BORV1:BORV0 = 01 BORV1:BORV0 = 00 D005 PIC18FXX39 BORV1:BORV0 = 1x BORV1:BORV0 = 01 BORV1:BORV0 = 00
2.0 4.2 1.5 --
-- -- -- --
5.5 5.5 -- 0.7
V V V V
HS Osc mode
See Section 3.1 (Power-on Reset) for details
D004
SVDD
0.05
--
--
V/ms See Section 3.1 (Power-on Reset) for details
VBOR D005
Brown-out Reset Voltage 1.98 2.67 4.16 4.45 N.A. 4.16 4.45 -- -- -- -- -- -- -- 2.14 2.89 4.5 4.83 N.A. 4.5 4.83 V V V V V V V Not in operating voltage range of device 85C T 25C
Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 4: The LVD and BOR modules share a large portion of circuitry. The IBOR and ILVD currents are not additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 261
PIC18FXX39
23.1 DC Characteristics: PIC18FXX39 (Industrial, Extended) PIC18LFXX39 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC18LFXX39 (Industrial) PIC18FXX39 (Industrial, Extended) Param Symbol No. IDD D010C D010C D013 Characteristic Supply Current(2) PIC18LFXX39
-- PIC18FXX39 -- PIC18LFXX39 -- -- D013 PIC18FXX39 -- -- IPD D020 Power-down Current(3) -- -- -- -- -- -- PIC18LFXX39
10 10 10 15 10 15 0.08 0.1 3 .1 3 15
25 25 15 25 15 25 0.9 4 10 .9 10 25
mA mA mA mA mA mA A A A A A A
EC, ECIO osc configurations VDD = 4.2V, -40C to +85C EC, ECIO osc configurations VDD = 4.2V, -40C to +125C HS osc configuration FOSC = 25 MHz, VDD = 5.5V HS + PLL osc configurations FOSC = 10 MHz, VDD = 5.5V HS osc configuration FOSC = 25 MHz, VDD = 5.5V HS + PLL osc configurations FOSC = 10 MHz, VDD = 5.5V VDD = 2.0V, +25C VDD = 2.0V, -40C to +85C VDD = 4.2V, -40C to +85C VDD = 4.2V, +25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C
D020 D021B
PIC18FXX39
Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 4: The LVD and BOR modules share a large portion of circuitry. The IBOR and ILVD currents are not additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
DS30485A-page 262
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
23.1 DC Characteristics: PIC18FXX39 (Industrial, Extended) PIC18LFXX39 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC18LFXX39 (Industrial) PIC18FXX39 (Industrial, Extended) Param Symbol No. D022 IWDT Characteristic
Module Differential Current Watchdog Timer PIC18LFXX39 Watchdog Timer PIC18FXX39 Brown-out Reset(4) PIC18LFXX39 Brown-out Reset(4) PIC18FXX39 Low Voltage Detect(4) PIC18LFXX39 Low Voltage Detect(4) PIC18FXX39 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.75 2 10 7 10 25 29 29 33 36 36 36 29 29 33 33 33 33 1.5 8 25 15 25 40 35 45 50 40 50 65 35 45 50 40 50 65 A A A A A A A A A A A A A A A A A A VDD = 2.0V, +25C VDD = 2.0V, -40C to +85C VDD = 4.2V, -40C to +85C VDD = 4.2V, +25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C VDD = 2.0V, +25C VDD = 2.0V, -40C to +85C VDD = 4.2V, -40C to +85C VDD = 4.2V, +25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C VDD = 2.0V, +25C VDD = 2.0V, -40C to +85C VDD = 4.2V, -40C to +85C VDD = 4.2V, +25C VDD = 4.2V, -40C to +85C VDD = 4.2V, -40C to +125C
D022
D022A IBOR
D022A
D022B ILVD
D022B
Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). 4: The LVD and BOR modules share a large portion of circuitry. The IBOR and ILVD currents are not additive. Once one of these modules is enabled, the other may also be enabled without further penalty.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 263
PIC18FXX39
23.2 DC Characteristics: PIC18FXX39 (Industrial, Extended) PIC18LFXX39 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Input Low Voltage I/O ports: D030 D030A D031 D032 D032A D033 VIH D040 D040A D041 D042 D042A IIL D060 D061 D063 IPU D070 IPURB with Schmitt Trigger buffer RC3 and RC4 MCLR, OSC1 (EC mode) OSC1 (HS mode) Input Leakage Current(1,2) I/O ports MCLR OSC1 Weak Pull-up Current PORTB weak pull-up current 50 450 A VDD = 5V, VPIN = VSS .02 -- -- 1 1 1 A A A VSS VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 (HS mode) OSC1 (EC mode) Input High Voltage I/O ports: with TTL buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.7 VDD 0.8 VDD 0.7 VDD VDD VDD VDD VDD VDD VDD V V V V V V VDD < 4.5V 4.5V VDD 5.5V with TTL buffer Vss -- Vss Vss VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.3 VDD 0.2 VDD 0.3 VDD 0.2 VDD V V V V V V V VDD < 4.5V 4.5V VDD 5.5V Min Max Units Conditions
DC CHARACTERISTICS Param Symbol No. VIL
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Parameter is characterized but not tested.
DS30485A-page 264
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
23.2 DC Characteristics: PIC18FXX39 (Industrial, Extended) PIC18LFXX39 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Output Low Voltage I/O ports -- -- VOH D090 D090A D150 VOD Open Drain High Voltage Capacitive Loading Specs on Output Pins D100(3) COSC2 D101 D102 CIO CB OSC2 pin All I/O pins SCL, SDA
--
DC CHARACTERISTICS Param Symbol No. VOL D080 D080A Output High Voltage(2) I/O ports
Min
Max
Units
Conditions
0.6 0.6
V V
IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C RA4 pin
VDD - 0.7 VDD - 0.7 --
-- -- 8.5
V V V
15 50 400
pF pF pF
In HS mode when external clock is used to drive OSC1 To meet the AC Timing Specifications In I2C mode
-- --
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as current sourced by the pin. 3: Parameter is characterized but not tested.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 265
PIC18FXX39
FIGURE 23-3: LOW VOLTAGE DETECT CHARACTERISTICS
VDD (LVDIF can be cleared in software)
VLVD (LVDIF set by hardware)
37 LVDIF
TABLE 23-1:
LOW VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended
Param Symbol No. D420 VLVD
Characteristic LVD Voltage on VDD LVV = 0001 transition high to LVV = 0010 low LVV = 0011 LVV = 0100 LVV = 0101 LVV = 0110 LVV = 0111 LVV = 1000 LVV = 1001 LVV = 1010 LVV = 1011 LVV = 1100 LVV = 1101 LVV = 1110
Min 1.98 2.18 2.37 2.48 2.67 2.77 2.98 3.27 3.47 3.57 3.76 3.96 4.16 4.45
Typ 2.06 2.27 2.47 2.58 2.78 2.89 3.1 3.41 3.61 3.72 3.92 4.13 4.33 4.64
Max 2.14 2.36 2.57 2.68 2.89 3.01 3.22 3.55 3.75 3.87 4.08 4.3 4.5 4.83
Units V V V V V V V V V V V V V V
Conditions T 25C T 25C T 25C
DS30485A-page 266
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
TABLE 23-2: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Internal Program Memory Programming Specifications D110 D113 VPP IDDP Voltage on MCLR/VPP pin Supply Current during Programming Data EEPROM Memory D120 D121 ED VDRW Cell Endurance VDD for Read/Write 100K VMIN
1M -- --
DC Characteristics Param No. Sym
Min
Typ
Max
Units
Conditions
9.00 --
-- --
13.25 10
V mA
E/W -40C to +85C V Using EECON to read/write VMIN = Minimum operating voltage
5.5
D122 D123
TDEW
Erase/Write Cycle Time
--
4 -- -- 10M
--
ms Year Provided no other specifications are violated Year 25C (Note 1) E/W -40C to +85C
TRETD Characteristic Retention
40
100
--
--
D123A TRETD Characteristic Retention D124 TREF Number of Total Erase/Write Cycles before Refresh(2) Program FLASH Memory D130 D131 D132 EP VPR VIE Cell Endurance VDD for Read VDD for Block Erase VDD for Externally Timed Erase or Write VDD for Self-timed Write ICSP Block Erase Cycle Time ICSP Erase or Write Cycle Time (externally timed) Self-timed Write Cycle Time
1M
--
10K VMIN 4.5 4.5 VMIN
--
100K
-- -- -- --
--
E/W -40C to +85C V V V V ms ms ms Year Provided no other specifications are violated Year 25C (Note 1) VMIN = Minimum operating voltage Using ICSP port Using ICSP port VMIN = Minimum operating voltage VDD 4.5V VDD 4.5V
5.5 5.5 5.5 5.5
-- -- --
D132A VIW D132B VPEW D133 TIE
4
--
D133A TIW D133A TIW D134
1
--
2 -- --
TRETD Characteristic Retention
40
100
--
--
D134A TRETD Characteristic Retention
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Retention time is valid, provided no other specifications are violated. 2: Refer to Section 6.8 for a more detailed discussion on data EEPROM endurance.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 267
PIC18FXX39
23.3
23.3.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T13CKI WR
P R V Z High Low
Period Rise Valid Hi-impedance High Low
SU STO
Setup STOP condition
DS30485A-page 268
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
23.3.2 TIMING CONDITIONS
The temperature and voltages specified in Table 23-3 apply to all timing specifications unless otherwise noted. Figure 23-4 specifies the load conditions for the timing specifications.
TABLE 23-3:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 23.1 and Section 23.2. LC parts operate for industrial temperatures only.
AC CHARACTERISTICS
FIGURE 23-4:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 VDD/2 RL Pin VSS Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports CL Load condition 2
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 269
PIC18FXX39
23.3.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 23-5:
OSC1
1 2 3 3 4 4
CLKO
TABLE 23-4:
Param. No. 1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKI Frequency(1) Oscillator Frequency(1) Min DC DC 4 4 4 Max 40 25 25 10 6.25 -- -- 250 250 250 -- -- -- 7.5 Units MHz MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns Conditions EC, ECIO, -40C to +85C EC, ECIO, +85C to +125C HS osc HS + PLL osc, -40C to +85C HS + PLL osc, +85C to +125C EC, ECIO, -40C to +85C EC, ECIO, +85C to +125C HS osc HS + PLL osc, -40C to +85C HS + PLL osc, +85C to +125C TCY = 4/FOSC, -40C to +85C TCY = 4/FOSC, +85C to +125C HS osc HS osc
Symbol FOSC
1
TOSC
External CLKI Period(1) Oscillator Period(1)
25 40 40 100 160
2 3 4
TCY TosL, TosH TosR, TosF
Instruction Cycle
Time(1)
100 160 10 --
External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
TABLE 23-5:
Param No. -- -- -- -- Sym
PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V)
Characteristic Min 4 16 -- -2 Typ -- -- -- -- Max 10 40 2 +2 Units Conditions
FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency trc CLK PLL Start-up Time (Lock Time) CLKO Stability (Jitter)
MHz HS mode only MHz HS mode only ms %
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS30485A-page 270
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 23-6: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 14 I/O Pin (input) 17 I/O Pin (output) Old Value 20, 21 Note: Refer to Figure 23-4 for load conditions. 15 New Value 19 18 12 16 11 Q1 Q2 Q3
TABLE 23-6:
Param. Symbol No. 10 11 12 13 14 15 16 17 18 18A 19 20 20A 21 21A 22 23 24 TINP TRBP TRCP TioF TioR
CLKO AND I/O TIMING REQUIREMENTS
Characteristic Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 200 0 -- -- -- -- TCY TCY 20 Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5 TCY + 20 -- -- 150 -- -- -- 25 60 25 60 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 2V VDD = 2V (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckL OSC1 to CLKO TosH2ckH OSC1 to CLKO TckR TckF CLKO rise time CLKO fall time
TckL2ioV CLKO to Port out valid TioV2ckH Port in valid before CLKO TckH2ioI TosH2ioI Port in hold after CLKO OSC1 (Q2 cycle) to Port PIC18FXXXX input invalid (I/O in hold time) PIC18LFXXXX Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time RC7:RC4 change INT high or low time PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX TosH2ioV OSC1 (Q1 cycle) to Port out valid
TioV2osH Port input valid to OSC1 (I/O in setup time)
These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 271
PIC18FXX39
FIGURE 23-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins Note: Refer to Figure 23-4 for load conditions. 33 32 30
31
34
FIGURE 23-8:
VDD
BROWN-OUT RESET TIMING
BVDD 35 VBGAP = 1.2V Typical
VIRVST Enable Internal Reference Voltage Internal Reference Voltage stable 36
TABLE 23-7:
Param. No. 30 31 32 33 34 35 36 37
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Postscaler) Oscillation Start-up Timer Period Power up Timer Period I/O high impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become stable Low Voltage Detect Pulse Width Min 2 7 1024 TOSC 28 -- 200 -- 200 Typ -- 18 -- 72 2 -- 20 -- Max -- 33 1024 TOSC 132 -- -- 500 -- Units s ms -- ms s s s s VDD VLVD (see D420) VDD BVDD (see D005) TOSC = OSC1 period Conditions
Symbol TmcL TWDT TOST TPWRT TIOZ TBOR TIVRST TLVD
DS30485A-page 272
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 23-9:
T0CKI
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
40 42 T13CKI
41
45 47 TMR0 or TMR1 Note: Refer to Figure 23-4 for load conditions.
46
48
TABLE 23-8:
Param Symbol No. 40 41 42 Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 10 Greater of: 20 nS or TCY + 40 N 0.5TCY + 20 10 25 30 50 0.5TCY + 5 10 25 30 50 Greater of: 20 nS or TCY + 40 N 60 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions
45
Tt1H
T13CKI High Time
Synchronous, no prescaler Synchronous, with prescaler Asynchronous PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8)
46
Tt1L
T13CKI Low Time
Synchronous, no prescaler Synchronous, with prescaler Asynchronous PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
47
Tt1P
T13CKI input period
Synchronous
Asynchronous Ft1 48 T13CKI oscillator input frequency range Tcke2tmrI Delay from external T13CKI clock edge to timer increment
-- 50 7 TOSC
ns kHz --
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 273
PIC18FXX39
FIGURE 23-10: PWM TIMINGS (PWM1 AND PWM2)
PWMx Output 53 Note: Refer to Figure 23-4 for load conditions. 54
TABLE 23-9:
Param. Symbol No. 53 54 TccR TccF
PWM TIMING REQUIREMENTS (PWM1 AND PWM2)
Characteristic PWMx Output Rise Time PWMx Output Fall Time PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX Min -- -- -- -- Max 25 60 25 60 Units ns ns ns ns VDD = 2V VDD = 2V Conditions
DS30485A-page 274
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 23-11:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC18F4X39)
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 23-4 for load conditions.
64
TABLE 23-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X39)
Param. No. 62 63 64 65 66 Symbol Characteristic Min 20 25 20 35 -- -- 10 -- Max -- -- -- -- 80 90 30 3 TCY Units ns ns ns ns ns ns ns VDD = 2V Extended Temp. Range Conditions
TdtV2wrH Data in valid before WR or CS (setup time) TwrH2dtI TrdL2dtV TrdH2dtI TibfINH WR or CS to data-in invalid PIC18FXXXX (hold time) PIC18LFXXXX RD and CS to data-out valid RD or CS to data-out invalid Inhibit of the IBF flag bit being cleared from WR or CS
Extended Temp. Range
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 275
PIC18FXX39
FIGURE 23-12:
SS 70 SCK (CKP = 0) 71 72 78 79
EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SCK (CKP = 1) 79 MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 23-4 for load conditions. bit6 - - - -1 LSb In bit6 - - - - - -1 78 LSb
80 SDO
TABLE 23-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param. No. 70 71 71A 72 72A 73 73A 74 75 76 78 79 80 TscL Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- -- -- -- -- -- -- -- -- -- Max Units Conditions -- -- -- -- -- -- -- -- 25 60 25 60 25 60 25 60 50 150 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 2V VDD = 2V VDD = 2V VDD = 2V VDD = 2V (Note 2) (Note 1) (Note 1)
TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time (Slave mode) SCK input low time (Slave mode)
TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL TB2B Last clock edge of Byte 1 to the 1st clock edge of Byte 2 TscH2diL, Hold time of SDI data input to SCK edge TscL2diL TdoR TdoF TscR TscF SDO data output rise time SDO data output fall time SCK output rise time (Master mode) PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX PIC18LFXXXX TscH2doV, SDO data output valid after SCK TscL2doV edge PIC18FXXXX PIC18LFXXXX
SCK output fall time (Master mode) PIC18FXXXX
Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used.
DS30485A-page 276
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 23-13:
SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 MSb 75, 76 SDI MSb In 74 Note: Refer to Figure 23-4 for load conditions. bit6 - - - -1 LSb In bit6 - - - - - -1 LSb 72 79
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SDO
TABLE 23-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param. No. 71 71A 72 72A 73 73A 74 75 76 78 79 80 81 TscL Symbol TscH Characteristic SCK input high time (Slave mode) SCK input low time (Slave mode) Continuous Single Byte Continuous Single Byte Min 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- -- -- -- -- -- -- -- -- -- TCY Max Units Conditions -- -- -- -- -- -- -- 25 60 25 60 25 60 25 60 50 150 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 2V VDD = 2V VDD = 2V VDD = 2V VDD = 2V (Note 2) (Note 1) (Note 1)
TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TscR TscF Last clock edge of Byte 1 to the 1st clock edge of Byte 2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX SCK output rise time (Master mode) PIC18FXXXX PIC18LFXXXX SCK output fall time (Master mode) PIC18FXXXX PIC18LFXXXX TscH2doV, SDO data output valid after SCK TscL2doV edge TdoV2scH, SDO data output setup to SCK edge TdoV2scL PIC18FXXXX PIC18LFXXXX
Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 277
PIC18FXX39
FIGURE 23-14:
SS 70 SCK (CKP = 0) 71 72 78 79 83
EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SCK (CKP = 1) 79 MSb 75, 76 SDI 73 Note: MSb In 74 bit6 - - - -1 LSb In bit6 - - - - - -1 78 LSb 77
80 SDO
Refer to Figure 23-4 for load conditions.
TABLE 23-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0))
Param. No. 70 71 71A 72 72A 73 73A 74 75 76 77 78 79 80 83 Symbol TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF Characteristic SS to SCK or SCK input SCK input high time (Slave mode) Continuous Single Byte SCK input low time (Slave mode) Continuous Single Byte Setup time of SDI data input to SCK edge Min TCY 1.25 TCY + 30 40 1.25 TCY + 30 40 100 1.5 TCY + 40 100 -- -- -- -- 10 -- -- -- -- -- -- 1.5 TCY + 40 Max -- -- -- -- -- -- -- -- 25 60 25 60 50 25 60 25 60 50 150 -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note 1) (Note 1)
Last clock edge of Byte 1 to the first clock edge of Byte 2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) SCK output fall time (Master mode) PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
(Note 2)
VDD = 2V VDD = 2V
VDD = 2V VDD = 2V VDD = 2V
TscH2doV, SDO data output valid after SCK edge PIC18FXXXX TscL2doV PIC18LFXXXX
TscH2ssH, SS after SCK edge TscL2ssH Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used.
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 23-15:
SS 70 83 71 72
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SCK (CKP = 0)
SCK (CKP = 1) 80 SDO MSb 75, 76 SDI MSb In 74 Note: Refer to Figure 23-4 for load conditions. bit6 - - - -1 LSb In bit6 - - - - - -1 LSb 77
TABLE 23-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param. No. 70 71 71A 72 72A 73A 74 75 76 77 78 79 80 82 83 TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscL Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte 1.25 TCY + 30 40 1.25 TCY + 30 40 100 -- -- -- -- 10 PIC18FXXXX PIC18LFXXXX SCK output fall time (Master mode) PIC18FXXXX PIC18LFXXXX TscH2doV, SDO data output valid after SCK TscL2doV edge TssL2doV PIC18FXXXX PIC18LFXXXX PIC18LFXXXX TscH2ssH, SS after SCK edge TscL2ssH -- -- -- -- -- -- -- -- 1.5 TCY + 40 Max -- -- -- -- -- -- -- 25 60 25 60 50 25 60 25 60 50 150 50 150 -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 2) (Note 1)
TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time (Slave mode) SCK input low time (Slave mode)
Last clock edge of Byte 1 to the first clock edge of Byte 2 1.5 TCY + 40 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
VDD = 2V VDD = 2V
VDD = 2V VDD = 2V VDD = 2V VDD = 2V
SDO data output valid after SS edge PIC18FXXXX
Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 279
PIC18FXX39
FIGURE 23-16: I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition
STOP Condition
Note:
Refer to Figure 23-4 for load conditions.
TABLE 23-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param. Symbol No. 90 91 92 93 TSU:STA THD:STA TSU:STO Setup time START condition Hold time STOP condition Setup time THD:STO STOP condition Hold time Characteristic START condition 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Max -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated
FIGURE 23-17:
I2C BUS DATA TIMING
103 100 101 102
SCL
90 91
106
107 92
SDA In
110 109 109
SDA Out Note: Refer to Figure 23-4 for load conditions.
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PIC18FXX39
TABLE 23-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
Param. No. Symbol Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module Min 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 1000 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 to 400 pF VDD 4.2V VDD 4.2V Only relevant for Repeated START condition After this period, the first clock pulse is generated s s PIC18FXXX must operate at a minimum of 1.5 MHz PIC18FXXX must operate at a minimum of 10 MHz Units s s Conditions PIC18FXXX must operate at a minimum of 1.5 MHz PIC18FXXX must operate at a minimum of 10 MHz
100
THIGH
101
TLOW
Clock low time
100 kHz mode 400 kHz mode SSP Module
102
TR
SDA and SCL rise time SDA and SCL fall time START condition setup time
100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
103 90 91 106 107 92 109 110
TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
START condition hold 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time 100 kHz mode 400 kHz mode STOP condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
D102
CB
Bus capacitive loading
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 281
PIC18FXX39
FIGURE 23-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 23-4 for load conditions.
STOP Condition
TABLE 23-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS
Param. Symbol No. 90 TSU:STA Characteristic START condition Setup time 91 THD:STA START condition Hold time 92 TSU:STO STOP condition Setup time 93 THD:STO STOP condition Hold time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) Note 1: Maximum pin capacitance = 10 pF for all I2C Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) pins. Max -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns Units ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated
FIGURE 23-19:
MASTER SSP I2C BUS DATA TIMING
103 100 101 102
SCL SDA In
90
91
106
107
92
109
109
110
SDA Out Note: Refer to Figure 23-4 for load conditions.
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2002 Microchip Technology Inc.
PIC18FXX39
TABLE 23-18: MASTER SSP I2C BUS DATA REQUIREMENTS
Param. Symbol No. 100 THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode 1 MHz mode(1) 101 TLOW Clock low time 100 kHz mode 400 kHz mode 1 MHz 102 TR SDA and SCL rise time SDA and SCL fall time mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 103 90 TF TSU:STA 100 kHz mode 400 kHz mode Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- 20 + 0.1 CB -- -- 20 + 0.1 CB 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 0 0 250 100 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 -- I2C Max -- -- -- -- -- -- 1000 300 300 1000 300 -- -- -- -- -- -- -- 0.9 -- -- -- -- -- 3500 1000 -- -- -- 400 Units ms ms ms ms ms ms ns ns ns ns ns ms ms ms ms ms ms ns ms ns ns ms ms ms ns ns ns ms ms pF Time the bus must be free before a new transmission can start (Note 2) VDD 4.2V VDD 4.2V Only relevant for Repeated START condition After this period, the first clock pulse is generated CB is specified to be from 10 to 400 pF Conditions
START condition 100 kHz mode setup time 400 kHz mode 1 MHz mode(1)
91
THD:STA START condition 100 kHz mode hold time 400 kHz mode 1 MHz mode(1) THD:DAT Data input hold time TSU:DAT Data input setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 1 MHz mode(1)
106 107 92
TSU:STO STOP condition setup time TAA
109
Output valid from 100 kHz mode clock 400 kHz mode 1 MHz mode
(1)
110
TBUF
Bus free time
100 kHz mode 400 kHz mode
D102
CB
Bus capacitive loading
Note 1: Maximum pin capacitance = 10 pF for all pins. 2: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line is released.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 283
PIC18FXX39
FIGURE 23-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK pin RC7/RX/DT pin 120 Note:
121
121
122
Refer to Figure 23-4 for load conditions.
TABLE 23-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param. No. 120 Symbol Characteristic PIC18FXXXX PIC18LFXXXX 121 122 Tckr Tdtr Clock out rise time and fall time (Master mode) Data out rise time and fall time PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX Min -- -- -- -- -- -- Max 50 150 25 60 25 60 Units ns ns ns ns ns ns VDD = 2V VDD = 2V VDD = 2V Conditions
TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid
FIGURE 23-21:
RC6/TX/CK pin RC7/RX/DT pin
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 23-4 for load conditions.
TABLE 23-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param. Symbol No. 125 126 Characteristic Min 10 PIC18FXXXX PIC18LFXXXX 15 20 Max -- -- -- Units ns ns ns VDD = 2V Conditions
TdtV2ckl SYNC RCV (MASTER & SLAVE) Data hold before CK (DT hold time) TckL2dtl Data hold after CK (DT hold time)
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Preliminary
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PIC18FXX39
TABLE 23-21: A/D CONVERTER CHARACTERISTICS: PIC18FXX39 (INDUSTRIAL, EXTENDED) PIC18LFXX39 (INDUSTRIAL)
Param Symbol No. A01 A03 A04 A05 A06 A10 A20 A20A A21 A22 A25 A30 A50 NR EIL EDL EG EOFF -- VREF VREFH VREFL VAIN ZAIN IREF Characteristic Resolution Integral linearity error Differential linearity error Gain error Offset error Monotonicity Reference Voltage (VREFH - VREFL) Reference voltage High Reference voltage Low Analog input voltage Recommended impedance of analog voltage source VREF input current (Note 1) 1.8V 3V AVSS AVSS - 0.3V AVSS - 0.3V -- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- guaranteed -- -- -- -- -- -- -- --
(2)
Max 10 <1 <1 <1 <1.5 -- -- AVDD + 0.3V VREFH AVDD + 0.3V 2.5 5 150
Units bit
Conditions
LSb VREF = VDD = 5.0V LSb VREF = VDD = 5.0V LSb VREF = VDD = 5.0V LSb VREF = VDD = 5.0V -- V V V V V k A A VDD 2.5V (Note 3) (Note 4) During VAIN acquisition During A/D conversion cycle VSS VAIN VREF VDD < 3.0V VDD 3.0V
Note 1: 2: 3: 4:
Vss VAIN VREF The A/D conversion result never decreases with an increase in the Input Voltage, and has no missing codes. For VDD < 2.5V, VAIN should be limited to < .5 VDD. Maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times.
FIGURE 23-22:
A/D CONVERSION TIMING
BSF ADCON0, GO (Note 2) Q4 A/D CLK 132 131 130
A/D DATA
9
8
7
...
...
2
1
0
ADRES ADIF GO
OLD_DATA
NEW_DATA TCY DONE
SAMPLE
SAMPLING STOPPED
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 285
PIC18FXX39
TABLE 23-22: A/D CONVERSION REQUIREMENTS
Param Symbol No. 130 131 132 135 TAD TCNV TACQ TSWC Characteristic A/D clock period PIC18FXXXX PIC18LFXXXX Conversion time (not including acquisition time) (Note 1) Acquisition time (Note 2) Switching Time from convert sample Min 1.6 2.0 11 5 10 -- Max 20(4) 6.0 12 -- -- (Note 3) Units s s TAD s s
VREF = VDD = 5.0V VREF = VDD = 2.5V
Conditions TOSC based A/D RC mode
Note 1: ADRES register may be read on the following TCY cycle. 2: The time for the holding capacitor to acquire the "New" input voltage, when the new input value has not changed by more than 1 LSB from the last sampled voltage. The source impedance (RS) on the input channels is 50. See Section 18.0 for more information on acquisition time consideration. 3: On the next Q4 cycle of the device clock. 4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
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2002 Microchip Technology Inc.
PIC18FXX39
24.0
Note:
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 24-1:
12
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
10
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V
5.0V 8
4.5V 4.0V
IDD (mA)
6 3.5V
4
3.0V
2
2.5V
2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (M H z)
FIGURE 24-2:
12
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
5.5V
10
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.0V
4.5V 8 4.0V IDD (mA)
3.5V 6
4
3.0V
2
2.5V
2.0V 0 4 6 8 10 12 14 16 18 20 22 24 26 FOSC (M H z)
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 287
PIC18FXX39
FIGURE 24-3:
20
TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
18
16
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V 5.0V 4.5V
14
12 IDD (mA) 10
4.2V
8
6
4
2
0 4 5 6 7 FOSC (MHz) 8 9 10
FIGURE 24-4:
20
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)
18 16
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V
5.0V 4.5V
14
12 IDD (mA) 4.2V 10
8
6 4
2
0 4 5 6 7 FOSC (MHz) 8 9 10
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 24-5:
16
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
14
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V
5.0V 12 4.5V 10 IDD (mA) 4.0V 8 4.2V
6
3.5V
4 3.0V 2
2.5V 2.0V 4 8 12 16 20 FOSC (MHz) 24 28 32 36 40
0
FIGURE 24-6:
16
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
14
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V
5.0V 12 4.5V 10 IDD (mA) 4.2V 4.0V
8 3.5V 6
4
3.0V
2 2.0V 0 4 8 12
2.5V
16
20 FOSC (MHz)
24
28
32
36
40
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 289
PIC18FXX39
FIGURE 24-7:
100
IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED)
Max (-40C to +125C) 10 Max (+85C) IPD (uA)
1
Typ (+25C) 0.1
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
0.01 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 24-8:
90
IBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00 - 2.16V)
80
70
60
Device Device Held in Held in RESET Reset
Max (+125C) Max (125C)
IDD (A)
50
Max (+85C) Max (85C)
40
Typ (+25C) Typ (25C)
30
20
Device Device in in SLEEP Sleep
10
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 24-9:
70
TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)
60
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
50
40 IPD (A)
Max (+125C) Max (125C)
30
Max (+85C) Max (85C)
20
10
Typ (+25C) Typ (25C)
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 24-10:
50
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)
45
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
40
35
Max Max (+125C) (125C) Max MAX (+85C) (85C)
WDT Period (ms)
30
25
Typ (+25C) (25C)
20
15
Min Min (-40C) (-40C)
10
5
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 291
PIC18FXX39
FIGURE 24-11:
90
ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5 - 4.78V)
80
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
Max (+125C) Max (125C)
70
60
Max (+125C) Max (125C)
IDD (A) 50
40
Typ (+25C) Typ (25C) Typ (+25C) Typ (25C)
30
20 LVDIF state is unknown 10 LVDIF is set by hardware 0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5
LVDIF can be cleared by firmware
5.0
5.5
FIGURE 24-12:
5.5 5.0 4.5
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C)
Max Max
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 5 10 IOH (-mA) 15 20 25
Typ (+25C) Typ (25C)
VOH (V)
Min Min
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 24-13:
3.0
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C)
2.5
2.0
Max Max
VOH (V)
1.5
Typ (+25C) Typ (25C)
1.0
Min Min
0.5
0.0 0 5 10 IOH (-mA) 15 20 25
FIGURE 24-14:
1.8
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C)
1.6
1.4
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
1.2
VOL (V)
1.0
Max Max
0.8
0.6
0.4
Typ (+25C) Typ (25C)
0.2
0.0 0 5 10 IOL (-mA) 15 20 25
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 293
PIC18FXX39
FIGURE 24-15:
2.5
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C)
2.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
1.5 VOL (V) 1.0
Max Max
Typ (+25C) Typ (25C)
0.5
0.0 0 5 10 IOL (-mA) 15 20 25
FIGURE 24-16:
4.0
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
3.5
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
VIH Max
3.0
2.5 VIH Min VIN (V) 2.0 VIL Max 1.5
1.0 VIL Min 0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
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2002 Microchip Technology Inc.
PIC18FXX39
FIGURE 24-17:
1.6
MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C)
1.4
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
VTH (Max)
1.2 VTH (Min) 1.0 VIN (V)
0.8
0.6
0.4
0.2
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 24-18:
3.5
MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C)
3.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
VIH Max
2.5
2.0 VIN (V)
VILMax VIH Min
1.5
1.0 VIL Min 0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 295
PIC18FXX39
FIGURE 24-19:
4
A/D NON-LINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C)
3.5
-40C -40C
Differential or Integral Nonlinearity (LSB) 3
+25C 25C
2.5
+85C 85C
2
1.5
1
0.5
+125C 125C
0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V)
FIGURE 24-20:
3
A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40C TO +125C)
2.5 Differential or Integral Nonlinearilty (LSB)
2
1.5
Max (-40Cto 125C) Max (-40C to +125C)
1
Typ (+25C) Typ (25C)
0.5
0 2 2.5 3 3.5 VREFH (V) 4 4.5 5 5.5
DS30485A-page 296
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
25.0
25.1
PACKAGING INFORMATION
Package Marking Information
28-Lead PDIP (Skinny DIP)
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F2439-I/SP 0217017
28-Lead SOIC
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F2439-E/SO
0210017
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 297
PIC18FXX39
Package Marking Information (Cont'd)
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F4439-I/P 0212017
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC18F4539 -E/PT 0220017
44-Lead QFN
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PIC18F4439 -I/ML 0220017
DS30485A-page 298
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
25.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-line (SP) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A c L A1 B1 B p
eB
Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom Dimension Limits n p A A2 A1 E E1 D L c B1 B eB MIN
INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 5 5 .310 .285 1.365 .130 .012 .053 .019 .350 10 10 .325 .295 1.385 .135 .015 .065 .022 .430 15 15 .150 .130 .160 .135 MAX MIN
MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 5 5 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 10 10 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 15 15 3.81 3.30 4.06 3.43 MAX
* Controlling Parameter Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-095
Drawing No. C04-070
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Preliminary
DS30485A-page 299
PIC18FXX39
28-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E p E1
D
B n h 45 c A Units Dimension Limits n p A A2 A1 E E1 D h L c B L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1
MIN
MAX
MIN
MAX
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
.093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0
.104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15
2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
40-Lead Plastic Dual In-line (P) - 600 mil (PDIP)
E1
D
n E
2 1
A c eB Units Dimension Limits n p INCHES* NOM 40 .100 .175 .150 A1 B1 B p MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10
A2 L
MIN
MAX
MIN
MAX
Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width .030 .050 .070 B1 Lower Lead Width B .014 .018 .022 eB Overall Row Spacing .620 .650 .680 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016
4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 301
PIC18FXX39
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E E1 #leads=n1 p
D1
D
B n
2 1
CH x 45 A
c
L
A1 (F)
A2
Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH
MIN
.039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5
INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10
MAX
MIN
.047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15
MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10
MAX
1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15
Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076
DS30485A-page 302
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)
E
EXPOSED METAL PAD
p D
D2
2 1 n OPTIONAL PIN 1 INDEX ON TOP MARKING PIN 1 INDEX ON EXPOSED PAD E2 L
B
TOP VIEW
BOTTOM VIEW
A A1 A3
Number of Pins Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length
Units Dimension Limits n p A A1 A3 E E2 D D2 B L
MIN
.031 .000
.262 .262 .012 .014
INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 BSC .268 .315 BSC .268 .013 .016
MAX
MIN
.039 .002
.274 .274 .013 .018
MILLIMETERS* NOM 44 0.65 BSC 0.90 0.80 0.02 0 0.25 REF 8.00 BSC 6.65 6.80 8.00 BSC 6.65 6.80 0.30 0.33 0.35 0.40
MAX
1.00 0.05
6.95 6.95 0.35 0.45
*Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: M0-220
Drawing No. C04-103
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 303
PIC18FXX39
44-Lead Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) Land Pattern and Solder Mask
M
B
M
p
PACKAGE EDGE SOLDER MASK
Pitch Pad Width Pad Length Pad to Solder Mask *Controlling Parameter
Drawing No. C04-2103
Units Dimension Limits p B L M
MIN __ __ .005
INCHES NOM .026 BSC __ __
MAX __ __ .006
MIN
MILLIMETERS* NOM 0.65 BSC __ __ __ __ 0.13
MAX __ __ 0.15
DS30485A-page 304
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
APPENDIX A: REVISION HISTORY APPENDIX B:
Revision A (November 2002)
Original data sheet for the PIC18FXX39 family.
DEVICE DIFFERENCES
The differences between the devices listed in this data sheet are shown in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Feature PIC18F2439 12 640 5 No 28-pin DIP 28-pin SOIC PIC18F2539 24 1408 5 No 28-pin DIP 28-pin SOIC PIC18F4439 12 640 8 Yes 40-pin DIP 44-pin TQFP 44-pin QFN PIC18F4539 24 1408 8 Yes 40-pin DIP 44-pin TQFP 44-pin QFN
Program Memory (Kbytes) Data Memory (Bytes) A/D Channels Parallel Slave Port (PSP) Package Types
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DS30485A-page 305
PIC18FXX39
APPENDIX C: CONVERSION CONSIDERATIONS
The considerations for converting applications from previous versions of PIC18 microcontrollers (i.e., PIC18FXX2 devices) are listed in Table C-1. A specific list of resources that are unavailable to PIC18FXX2 applications in PIC18FXX39 devices is presented in Table C-2.
TABLE C-1:
CONVERSION CONSIDERATIONS BETWEEN PIC18FXX2 AND PIC18FXX39 DEVICES
PIC18FXX2 28/40/44 DIP, PDIP, SOIC, PLCC, QFN, TQFP 2.0 - 5.5V DC - 40 MHz 16K or 32K 768 or 1536 256 17 or 18 Two levels: low priority (vector at 0008h) high priority (vector at 0018h) 4 yes yes 2 CCP no 10-bit, 5 or 8 channels, 7 conversion clock selects PSP, AUSART, MSSP (SPI and I2C) By 8K block with separate 512-byte boot block; protection from external reads and writes, Table Read and intra-block Table Read PIC18FXX39 28/40/44 DIP, PDIP, SOIC, QFN, TQFP 2.0 - 5.5V 4 - 40 MHz (20 MHz optimal) 12K or 24K 640 or 1408 256 15 or 16 One level when using Motor Control: vector at 0008h 3 no no 2 PWM only, available only through Motor Control kernel yes 10-bit, 5 or 8 channels, 7 conversion clock selects PSP, AUSART, MSSP (SPI and I2C) By 8K block with separate 512-byte boot block; protection from external reads and writes, Table Read and intrablock Table Read; Block 3 not protected on PIC18FX539
Characteristic Pins Available Packages Voltage Range Frequency Range Available Program Memory (bytes) Available Data RAM (bytes) Data EEPROM Interrupt Sources Interrupt Priority Levels
Timers (available to users) Timer1 Oscillator option Oscillator Switching Capture/Compare/PWM Motor Control Kernel A/D Communications Code Protection
TABLE C-2:
I/O Resources Registers SFR bits
UNAVAILABLE RESOURCES (COMPARED TO PIC18FXX2)
Item(s) RC1; RC2; T1OSO; T1OSI CCP1CON; CCP2CON; CCPR1L; CCPR2L; TMR2; PR2; T2CON; OSCCON CCP1IE; CCP1IF; CCP1IP; CCP21E; CCP21F; CCP2IP; T1OSCEN; T3CCP1; TMR2ON; TOUTPS<3:0>; T2CKPS<1:0>; T3CCP2; SFS; RC1; RC2; TRISC1; TRISC2; LATC1; LATC2 CCP1 Capture/Compare match; CCP2 Capture/Compare match; High priority interrupts (when Motor Control is used; reserved for Timer2) Timer2 (available only through the Motor Control kernel); Timer2 as a clock source for MSSP module (SPI mode) Capture and Compare functionality; Timer1 reset on special event; Timer3 reset on special event; A/D conversion on special event; Interrupt on special event OSCEN; CCP2MX; CP3; WRT3; EBTR3
Resource Type
Interrupts and Interrupt Resources Timer Resources CCP Resources Configuration Word bits
DS30485A-page 306
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
APPENDIX D: MIGRATION FROM HIGH-END TO ENHANCED DEVICES
A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration". This Application Note is available as Literature Number DS00726.
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Preliminary
DS30485A-page 307
PIC18FXX39
NOTES:
DS30485A-page 308
Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
INDEX
A
A/D ................................................................................... 181 A/D Converter Flag (ADIF Bit) ................................. 183 A/D Converter Interrupt, Configuring ....................... 184 Acquisition Requirements ........................................ 184 ADCON0 Register .................................................... 181 ADCON1 Register .................................................... 181 ADRESH Register .................................................... 181 ADRESH/ADRESL Registers .................................. 183 ADRESL Register .................................................... 181 Analog Port Pins .................................................. 95, 96 Analog Port Pins, Configuring .................................. 186 Associated Registers ............................................... 188 Configuring the Module ............................................ 184 Conversion Clock (TAD) ........................................... 186 Conversion Status (GO/DONE Bit) .......................... 183 Conversions ............................................................. 187 Converter Characteristics ........................................ 285 Equations Acquisition Time ............................................... 185 Minimum Charging Time .................................. 185 Examples Calculating the Minimum Required Acquisition Time ...................................... 185 Result Registers ....................................................... 187 TAD vs. Device Operating Frequencies .................... 186 Absolute Maximum Ratings ............................................. 259 AC (Timing) Characteristics ............................................. 268 Conditions ................................................................ 269 Load Conditions for Device Timing Specifications ....................................... 269 Parameter Symbology ............................................. 268 Temperature and Voltage Specifications ................. 269 ACKSTAT Status Flag ..................................................... 155 ADCON0 Register ............................................................ 181 GO/DONE Bit ........................................................... 183 ADCON1 Register ............................................................ 181 ADDLW ............................................................................ 217 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See USART ADDWF ............................................................................ 217 ADDWFC ......................................................................... 218 ADRESH Register ............................................................ 181 ADRESH/ADRESL Registers ........................................... 183 ADRESL Register ............................................................ 181 Analog-to-Digital Converter. See A/D ANDLW ............................................................................ 218 ANDWF ............................................................................ 219 Assembler MPASM Assembler .................................................. 253 Block Diagrams A/D Converter .......................................................... 183 Analog Input Model .................................................. 184 Baud Rate Generator .............................................. 151 Low Voltage Detect External Reference Source ............................. 190 Internal Reference Source ............................... 190 MSSP (I2C Mode) .................................................... 134 MSSP (SPI Mode) ................................................... 125 On-Chip Reset Circuit ................................................ 23 PIC18F2X39 ................................................................ 9 PIC18F4X39 .............................................................. 10 PLL ............................................................................ 21 PORTC (Peripheral Output Override) ........................ 89 PORTD (I/O Mode) .................................................... 91 PORTD and PORTE (Parallel Slave Port) ................. 96 PORTE (I/O Port Mode) ............................................. 93 PWM Operation (Simplified) .................................... 123 RA3:RA0 and RA5 Pins ............................................. 83 RA4/T0CKI Pin .......................................................... 84 RA6 Pin ..................................................................... 84 RB2:RB0 Pins ............................................................ 87 RB3 Pin ..................................................................... 87 RB7:RB4 Pins ............................................................ 86 Reads from FLASH Program Memory ....................... 55 Table Read Operation ............................................... 51 Table Write Operation ................................................ 52 Table Writes to FLASH Program Memory ................. 57 Timer0 in 16-bit Mode .............................................. 100 Timer0 in 8-bit Mode ................................................ 100 Timer1 ..................................................................... 104 Timer1 (16-bit R/W Mode) ....................................... 104 Timer2 ..................................................................... 107 Timer3 ..................................................................... 110 Timer3 (16-bit R/W Mode) ....................................... 110 Typical Motor Control System .................................. 113 USART Receive ....................................................... 174 USART Transmit ...................................................... 172 Watchdog Timer ...................................................... 204 BN .................................................................................... 220 BNC ................................................................................. 221 BNN ................................................................................. 221 BNOV ............................................................................... 222 BNZ .................................................................................. 222 BOR. See Brown-out Reset BOV ................................................................................. 225 BRA ................................................................................. 223 BRG. See Baud Rate Generator Brown-out Reset (BOR) ..................................................... 24 BSF .................................................................................. 223 BTFSC ............................................................................. 224 BTFSS ............................................................................. 224 BTG ................................................................................. 225 BZ .................................................................................... 226
B
Baud Rate Generator ....................................................... 151 BC .................................................................................... 219 BCF .................................................................................. 220 BF Status Flag ................................................................. 155
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Preliminary
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PIC18FXX39
C
CALL ................................................................................ 226 Clocking Scheme/Instruction Cycle .................................... 36 CLRF ................................................................................ 227 CLRWDT .......................................................................... 227 Code Examples 16 x 16 Signed Multiply Routine ................................. 68 16 x 16 Unsigned Multiply Routine ............................. 68 8 x 8 Signed Multiply Routine ..................................... 67 8 x 8 Unsigned Multiply Routine ................................. 67 Data EEPROM Read ................................................. 63 Data EEPROM Refresh Routine ................................ 64 Data EEPROM Write .................................................. 63 Erasing a FLASH Program Memory Row .................. 56 How to Clear RAM (Bank 1) Using Indirect Addressing ............................................ 47 Initializing PORTA ...................................................... 83 Initializing PORTB ...................................................... 86 Initializing PORTC ...................................................... 89 Initializing PORTD ...................................................... 91 Initializing PORTE ...................................................... 93 Loading the SSPBUF (SSPSR) Register ................. 128 Motor Control Routine using ProMPT APIs .............. 121 Reading a FLASH Program Memory Word ................ 55 Saving STATUS, WREG and BSR Registers in RAM ....................................... 81 Writing to FLASH Program Memory ..................... 58-59 Code Protection ............................................................... 195 COMF ............................................................................... 228 Configuration Bits ............................................................. 195 Context Saving During Interrupts ....................................... 81 Conversion Considerations .............................................. 306 CPFSEQ .......................................................................... 228 CPFSGT ........................................................................... 229 CPFSLT ........................................................................... 229 Device Overview .................................................................. 7 Features ....................................................................... 8 Direct Addressing ............................................................... 48 Example ..................................................................... 46
E
Electrical Characteristics .................................................. 259 Errata ................................................................................... 5
F
Firmware Instructions ....................................................... 211 FLASH Program Memory ................................................... 51 Associated Registers ................................................. 59 Control Registers ....................................................... 52 Erase Sequence ........................................................ 56 Erasing ....................................................................... 56 Operation During Code Protection ............................. 59 Reading ..................................................................... 55 TABLAT Register ....................................................... 54 Table Pointer ............................................................. 54 Boundaries Based on Operation ........................ 54 Table Pointer Boundaries .......................................... 54 Table Reads and Table Writes .................................. 51 Writing to .................................................................... 57 Protection Against Spurious Writes ................... 59 Unexpected Termination .................................... 59 Write Verify ........................................................ 59
G
GOTO .............................................................................. 232
H
Hardware Interface .......................................................... 113 Hardware Multiplier ............................................................ 67 Introduction ................................................................ 67 Operation ................................................................... 67 Performance Comparison .......................................... 67 HS/PLL .............................................................................. 20
D
Data EEPROM Memory Associated Registers ................................................. 65 EEADR Register ........................................................ 61 EECON1 Register ...................................................... 61 EECON2 Register ...................................................... 61 Operation During Code Protect .................................. 64 Protection Against Spurious Write ............................. 64 Reading ...................................................................... 63 Using .......................................................................... 64 Write Verify ................................................................. 64 Writing ........................................................................ 63 Data Memory ...................................................................... 39 General Purpose Registers ........................................ 39 Map for PIC18FX439 ................................................. 40 Map for PIC18FX539 ................................................. 41 Special Function Registers ........................................ 39 DAW ................................................................................. 230 DC and AC Characteristics Graphs and Tables ................................................... 287 DC Characteristics ................................................... 261, 264 DCFSNZ ........................................................................... 231 DECF ............................................................................... 230 DECFSZ ........................................................................... 231 Developing Applications ................................................... 121 Development Support ...................................................... 253 Device Differences ........................................................... 305
I
I/O Ports ............................................................................. 83 I2C Mode Bus Collision During a STOP Condition ................................ 163 I2C Mode .......................................................................... 134 ACK Pulse ........................................................138, 139 Acknowledge Sequence Timing .............................. 158 Baud Rate Generator ............................................... 151 Bus Collision Repeated START Condition ............................ 162 START Condition ............................................. 160 Clock Arbitration ...................................................... 152 Clock Stretching ....................................................... 144 Effect of a RESET .................................................... 159 General Call Address Support ................................. 148 Master Mode ............................................................ 149 Operation ......................................................... 150 Reception ........................................................ 155 Repeated START Condition Timing ................ 154 START Condition Timing ................................. 153 Transmission ................................................... 155 Multi-Master Communication, Bus Collision and Arbitration ................................................. 159
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Preliminary
2002 Microchip Technology Inc.
PIC18FXX39
Multi-Master Mode ................................................... 159 Operation ................................................................. 138 Read/Write Bit Information (R/W Bit) ............... 138, 139 Registers .................................................................. 134 Serial Clock (RC3/SCK/SCL) ................................... 139 Slave Mode .............................................................. 138 Addressing ....................................................... 138 Reception ......................................................... 139 Transmission .................................................... 139 SLEEP Operation ..................................................... 159 STOP Condition Timing ........................................... 158 ICEPIC In-Circuit Emulator .............................................. 254 ID Locations ............................................................. 195, 210 INCF ................................................................................. 232 INCFSZ ............................................................................ 233 In-Circuit Debugger .......................................................... 210 In-Circuit Serial Programming (ICSP) ...................... 195, 210 Indirect Addressing ............................................................ 48 INDF and FSR Registers ........................................... 47 Operation ................................................................... 47 Indirect Addressing Operation ............................................ 48 Indirect File Operand .......................................................... 39 INFSNZ ............................................................................ 233 Instruction Cycle ................................................................. 36 Instruction Flow/Pipelining ................................................. 37 Instruction Format ............................................................ 213 Instruction Set .................................................................. 211 ADDLW .................................................................... 217 ADDWF .................................................................... 217 ADDWFC ................................................................. 218 ANDLW .................................................................... 218 ANDWF .................................................................... 219 BC ............................................................................ 219 BCF .......................................................................... 220 BN ............................................................................ 220 BNC ......................................................................... 221 BNN ......................................................................... 221 BNOV ....................................................................... 222 BNZ .......................................................................... 222 BOV ......................................................................... 225 BRA .......................................................................... 223 BSF .......................................................................... 223 BTFSC ..................................................................... 224 BTFSS ..................................................................... 224 BTG .......................................................................... 225 BZ ............................................................................ 226 CALL ........................................................................ 226 CLRF ........................................................................ 227 CLRWDT .................................................................. 227 COMF ...................................................................... 228 CPFSEQ .................................................................. 228 CPFSGT .................................................................. 229 CPFSLT ................................................................... 229 DAW ......................................................................... 230 DCFSNZ .................................................................. 231 DECF ....................................................................... 230 DECFSZ ................................................................... 231 GOTO ...................................................................... 232 INCF ......................................................................... 232 INCFSZ .................................................................... 233 INFSNZ .................................................................... 233 IORLW ..................................................................... 234 IORWF ..................................................................... 234 LFSR ........................................................................ 235 MOVF ....................................................................... 235 MOVFF .................................................................... 236 MOVLB .................................................................... 236 MOVLW ................................................................... 237 MOVWF ................................................................... 237 MULLW .................................................................... 238 MULWF .................................................................... 238 NEGF ....................................................................... 239 NOP ......................................................................... 239 POP ......................................................................... 240 PUSH ....................................................................... 240 RCALL ..................................................................... 241 RESET ..................................................................... 241 RETFIE .................................................................... 242 RETLW .................................................................... 242 RETURN .................................................................. 243 RLCF ....................................................................... 243 RLNCF ..................................................................... 244 RRCF ....................................................................... 244 RRNCF .................................................................... 245 SETF ....................................................................... 245 SLEEP ..................................................................... 246 SUBFWB ................................................................. 246 SUBLW .................................................................... 247 SUBWF .................................................................... 247 SUBWFB ................................................................. 248 SWAPF .................................................................... 248 TBLRD ..................................................................... 249 TBLWT .................................................................... 250 TSTFSZ ................................................................... 251 XORLW ................................................................... 251 XORWF ................................................................... 252 Summary Table ....................................................... 214 Instructions in Program Memory ........................................ 37 Two-Word Instructions ............................................... 38 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register RBIF Bit ..................................................................... 86 INTCON Registers ........................................................71-73 Inter-Integrated Circuit. See I2C Interrupt Sources ............................................................. 195 A/D Conversion Complete ....................................... 184 INT0 ........................................................................... 81 Interrupt-on-Change (RB7:RB4) ................................ 86 PORTB, Interrupt-on-Change .................................... 81 RB0/INT Pin, External ................................................ 81 TMR0 ......................................................................... 81 TMR0 Overflow ........................................................ 101 TMR1 Overflow .................................................103, 105 TMR2 to PR2 Match (PWM) .................................... 123 TMR3 Overflow .................................................109, 111 USART Receive/Transmit Complete ....................... 165 Interrupts ............................................................................ 69 Logic .......................................................................... 70 Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) ................................. 183 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ........................................................... 86 IORLW ............................................................................. 234 IORWF ............................................................................. 234 IPR Registers ................................................................78-79
K
KEELOQ Evaluation and Programming Tools ................... 256
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PIC18FXX39
L
LFSR ................................................................................ 235 Lookup Tables Computed GOTO ....................................................... 38 Table Reads, Table Writes ......................................... 38 Low Voltage Detect .......................................................... 189 Characteristics ......................................................... 266 Effects of a RESET .................................................. 193 Operation ................................................................. 192 Current Consumption ....................................... 193 During SLEEP .................................................. 193 Reference Voltage Set Point ............................ 193 Typical Application ................................................... 189 LVD. See Low Voltage Detect. ......................................... 189
O
Opcode Field Descriptions ............................................... 212 OPTION_REG Register PSA Bit .................................................................... 101 T0CS Bit .................................................................. 101 T0PS2:T0PS0 Bits ................................................... 101 T0SE Bit ................................................................... 101 Oscillator Configuration ...................................................... 19 EC .............................................................................. 19 ECIO .......................................................................... 19 HS .............................................................................. 19 HS + PLL ................................................................... 19 Oscillator Selection .......................................................... 195 Oscillator, Timer1 ............................................................. 103 Oscillator, Timer3 ............................................................. 109 Oscillator, WDT ................................................................ 203
M
Master SSP (MSSP) Module Overview .................................................................. 125 Master Synchronous Serial Port (MSSP). See MSSP. Master Synchronous Serial Port. See MSSP Memory Organization Data Memory .............................................................. 39 Program Memory ....................................................... 33 Memory Programming Requirements .............................. 267 Migration from High-End to Enhanced Devices ............... 307 Motor Control ........................................................... 113, 121 ProMPT API Methods ...................................... 117-120 Defined Parameters ......................................... 121 Software Interface .................................................... 114 Theory of Operation ................................................. 113 V/F Curve ................................................................. 114 MOVF ............................................................................... 235 MOVFF ............................................................................. 236 MOVLB ............................................................................. 236 MOVLW ............................................................................ 237 MOVWF ........................................................................... 237 MPLAB C17 and MPLAB C18 C Compilers ..................... 253 MPLAB ICD In-Circuit Debugger ...................................... 255 MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE ....................................... 254 MPLAB Integrated Development Environment Software .............................................. 253 MPLINK Object Linker/MPLIB Object Librarian ............... 254 MSSP Control Registers (general) ...................................... 125 Enabling SPI I/O ....................................................... 129 I2C Mode. See I2C ................................................... 125 Operation ................................................................. 128 SPI Master Mode ..................................................... 130 SPI Master/Slave Connection .................................. 129 SPI Mode ................................................................. 125 SPI Slave Mode ....................................................... 131 SSPBUF Register .................................................... 130 SSPSR Register ....................................................... 130 Typical Connection ................................................... 129 MULLW ............................................................................ 238 MULWF ............................................................................ 238
P
Packaging ........................................................................ 297 Details ...................................................................... 299 Marking Information ................................................. 297 Parallel Slave Port (PSP) ..............................................91, 96 Associated Registers ................................................. 97 PORTD ...................................................................... 96 RE0/AN5/RD Pin ....................................................... 95 RE1/AN6/WR Pin ..................................................95, 96 RE2/AN7/CS Pin ...................................................95, 96 Select (PSPMODE Bit) .........................................91, 96 PIC18F2X39 Pin Functions MCLR/VPP ................................................................. 11 OSC1/CLKI ................................................................ 11 OSC2/CLKO/RA6 ...................................................... 11 PWM1 ........................................................................ 13 PWM2 ........................................................................ 13 RA0/AN0 .................................................................... 11 RA1/AN1 .................................................................... 11 RA2/AN2/VREF- ......................................................... 11 RA3/AN3/VREF+ ......................................................... 11 RA4/T0CKI ................................................................. 11 RA5/AN4/SS/LVDIN .................................................. 11 RB0/INT0 ................................................................... 12 RB1/INT1 ................................................................... 12 RB2/INT2 ................................................................... 12 RB3 ............................................................................ 12 RB4 ............................................................................ 12 RB5/PGM ................................................................... 12 RB6/PGC ................................................................... 12 RB7/PGD ................................................................... 12 RC0/T13CKI .............................................................. 13 RC3/SCK/SCL ........................................................... 13 RC4/SDI/SDA ............................................................ 13 RC5/SDO ................................................................... 13 RC6/TX/CK ................................................................ 13 RC7/RX/DT ................................................................ 13 VDD ............................................................................ 13 VSS ............................................................................. 13
N
NEGF ............................................................................... 239 NOP ................................................................................. 239
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2002 Microchip Technology Inc.
PIC18FXX39
PIC18F4X39 Pin Functions MCLR/VPP .................................................................. 14 OSC1/CLKI ................................................................ 14 OSC2/CLKO/RA6 ...................................................... 14 PWM1 ........................................................................ 16 PWM2 ........................................................................ 16 RA0/AN0 .................................................................... 14 RA1/AN1 .................................................................... 14 RA2/AN2/VREF- .......................................................... 14 RA3/AN3/VREF+ ......................................................... 14 RA4/T0CKI ................................................................. 14 RA5/AN4/SS/LVDIN ................................................... 14 RB0/INT ..................................................................... 15 RB1/INT1 ................................................................... 15 RB2/INT2 ................................................................... 15 RB3 ............................................................................ 15 RB4 ............................................................................ 15 RB5/PGM ................................................................... 15 RB6/PGC ................................................................... 15 RB7/PGD ................................................................... 15 RC0/T13CKI ............................................................... 16 RC3/SCK/SCL ........................................................... 16 RC4/SDI/SDA ............................................................ 16 RC5/SDO ................................................................... 16 RC6/TX/CK ................................................................ 16 RC7/RX/DT ................................................................ 16 RD0/PSP0 .................................................................. 17 RD1/PSP1 .................................................................. 17 RD2/PSP2 .................................................................. 17 RD3/PSP3 .................................................................. 17 RD4/PSP4 .................................................................. 17 RD5/PSP5 .................................................................. 17 RD6/PSP6 .................................................................. 17 RD7/PSP7 .................................................................. 17 RE0/AN5/RD .............................................................. 18 RE1/AN6/WR ............................................................. 18 RE2/AN7/CS .............................................................. 18 VDD ............................................................................. 18 VSS ............................................................................. 18 PIC18FXX39 Voltage-Frequency Graph (Industrial) ................................................................ 260 PIC18LFXX39 Voltage-Frequency Graph (Industrial) ................................................................ 260 PICDEM 1 Low Cost PICmicro Demonstration Board ............................................... 255 PICDEM 17 Demonstration Board ................................... 256 PICDEM 2 Low Cost PIC16CXX Demonstration Board ............................................... 255 PICDEM 3 Low Cost PIC16CXXX Demonstration Board ............................................... 256 PICSTART Plus Entry Level Development Programmer ............................................................. 255 PIE Registers ............................................................... 76-77 Pinout I/O Descriptions PIC18F2X39 .............................................................. 11 PIC18F4X39 .............................................................. 14 PIR Registers ............................................................... 74-75 PLL Lock Time-out ............................................................. 24 Pointer, FSR ....................................................................... 47 POP .................................................................................. 240 POR. See Power-on Reset PORTA Associated Registers ................................................. 85 LATA Register ........................................................... 83 PORTA Register ........................................................ 83 TRISA Register .......................................................... 83 PORTB Associated Registers ................................................. 88 LATB Register ........................................................... 86 PORTB Register ........................................................ 86 RB0/INT Pin, External ................................................ 81 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........................................................... 86 TRISB Register .......................................................... 86 PORTC Associated Registers ................................................. 90 LATC Register ........................................................... 89 PORTC Register ........................................................ 89 RC3/SCK/SCL Pin ................................................... 139 RC7/RX/DT Pin ........................................................ 168 TRISC Register ...................................................89, 165 PORTD Associated Registers ................................................. 92 LATD Register ........................................................... 91 Parallel Slave Port (PSP) Function ............................ 91 PORTD Register ........................................................ 91 TRISD Register .......................................................... 91 PORTE Analog Port Pins ...................................................95, 96 Associated Registers ................................................. 95 LATE Register ........................................................... 93 PORTE Register ........................................................ 93 PSP Mode Select (PSPMODE Bit) .......................91, 96 RE0/AN5/RD Pin ..................................................95, 96 RE1/AN6/WR Pin ..................................................95, 96 RE2/AN7/CS Pin ...................................................95, 96 TRISE Register .......................................................... 93 Postscaler, WDT Assignment (PSA Bit) .............................................. 101 Rate Select (T0PS2:T0PS0 Bits) ............................. 101 Switching Between Timer0 and WDT ...................... 101 Power-down Mode. See SLEEP Power-on Reset (POR) ...................................................... 24 Oscillator Start-up Timer (OST) ................................. 24 Power-up Timer (PWRT) ........................................... 24 Prescaler, Timer0 ............................................................ 101 Assignment (PSA Bit) .............................................. 101 Rate Select (T0PS2:T0PS0 Bits) ............................. 101 Switching Between Timer0 and WDT ...................... 101 Prescaler, Timer2 ............................................................ 124 PRO MATE II Universal Device Programmer .................. 255 Product Identification System .......................................... 319 Program Counter PCL Register ............................................................. 36 PCLATH Register ...................................................... 36 PCLATU Register ...................................................... 36 Program Memory Interrupt Vector .......................................................... 33 Map and Stack for PIC18FXX39 ................................ 33 RESET Vector ........................................................... 33 Program Verification and Code Protection ...................... 206 Associated Registers ............................................... 207 Configuration Register ............................................. 210 Data EEPROM ......................................................... 210 Program Memory ..................................................... 208
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Programming, Device Instructions ................................... 211 PSP.See Parallel Slave Port. Pulse Width Modulation (PWM) ....................................... 123 Pulse Width Modulation. See PWM. PUSH ............................................................................... 240 PWM Associated Registers ............................................... 124 CCPR1H:CCPR1L Registers ................................... 123 Duty Cycle ................................................................ 124 Period ....................................................................... 123 TMR2 to PR2 Match ................................................. 123 TXSTA (Transmit Status and Control) ..................... 166 WDTCON (Watchdog Timer Control) ...................... 203 RESET ................................................................23, 195, 241 Brown-out Reset (BOR) ........................................... 195 MCLR Reset (During SLEEP) .................................... 23 MCLR Reset (Normal Operation) .............................. 23 Oscillator Start-up Timer (OST) ............................... 195 Power-on Reset (POR) .......................................23, 195 Power-up Timer (PWRT) ......................................... 195 Programmable Brown-out Reset (BOR) .................... 23 RESET Instruction ..................................................... 23 Stack Full Reset ......................................................... 23 Stack Underflow Reset .............................................. 23 Watchdog Timer (WDT) Reset .................................. 23 RETFIE ............................................................................ 242 RETLW ............................................................................ 242 RETURN .......................................................................... 243 Return Address Stack ........................................................ 34 Associated Registers ................................................. 35 Pointer (STKPTR) ...................................................... 34 Top-of-Stack Access .................................................. 34 Revision History ............................................................... 305 RLCF ............................................................................... 243 RLNCF ............................................................................. 244 RRCF ............................................................................... 244 RRNCF ............................................................................ 245
Q
Q Clock ............................................................................ 124
R
RAM. See Data Memory RCALL .............................................................................. 241 RCSTA Register SPEN Bit .................................................................. 165 Register File ....................................................................... 39 Registers ADCON0 (A/D Control 0) ......................................... 181 ADCON1 (A/D Control 1) ......................................... 182 CCP1CON and CCP2CON (PWM Control) ............. 123 CONFIG1H (Configuration 1 High) .......................... 196 CONFIG2H (Configuration 2 High) .......................... 197 CONFIG2L (Configuration 2 Low) ............................ 197 CONFIG4L (Configuration 4 Low) ............................ 198 CONFIG5H (Configuration 5 High) .......................... 199 CONFIG5L (Configuration 5 Low) ............................ 199 CONFIG6H (Configuration 6 High) .......................... 200 CONFIG6L (Configuration 6 Low) ............................ 200 CONFIG7H (Configuration 7 High) .......................... 201 CONFIG7L (Configuration 7 Low) ............................ 201 DEVID1 (Device ID 1) .............................................. 202 DEVID2 (Device ID 2) .............................................. 202 EECON1 (Data EEPROM Control 1) ................... 53, 62 File Summary ....................................................... 43-45 INTCON (Interrupt Control) ........................................ 71 INTCON2 (Interrupt Control 2) ................................... 72 INTCON3 (Interrupt Control 3) ................................... 73 IPR1 (Peripheral Interrupt Priority 1) .......................... 78 IPR2 (Peripheral Interrupt Priority 2) .......................... 79 LVDCON (LVD Control) ........................................... 191 PIE1 (Peripheral Interrupt Enable 1) .......................... 76 PIE2 (Peripheral Interrupt Enable 2) .......................... 77 PIR1 (Peripheral Interrupt Request 1) ........................ 74 PIR2 (Peripheral Interrupt Request 2) ........................ 75 RCON (Register Control) ........................................... 80 RCON (RESET Control) ............................................. 50 RCSTA (Receive Status and Control) ...................... 167 SSPCON1 (MSSP Control 1) SPI Mode ......................................................... 127 SSPCON1 (MSSP Control 1), I2C Mode .................. 136 SSPCON2 (MSSP Control 2), I2C Mode .................. 137 SSPSTAT (MSSP Status) SPI Mode ......................................................... 126 SSPSTAT (MSSP Status), I2C Mode ....................... 135 STATUS ..................................................................... 49 STKPTR (Stack Pointer) ............................................ 35 T0CON (Timer0 Control) ............................................ 99 T1CON (Timer 1 Control) ......................................... 103 T2CON (Timer2 Control) .......................................... 107 T3CON (Timer3 Control) .......................................... 109 TRISE ......................................................................... 94
S
SCI. See USART SCK ................................................................................. 125 SDI ................................................................................... 125 SDO ................................................................................. 125 Serial Clock, SCK ............................................................ 125 Serial Communication Interface. See USART Serial Data In, SDI ........................................................... 125 Serial Data Out, SDO ....................................................... 125 Serial Peripheral Interface. See SPI Mode SETF ................................................................................ 245 Single Phase Induction Motor Control Module. See Motor Control. ................................................... 113 Slave Select Synchronization .......................................... 131 Slave Select, SS .............................................................. 125 SLEEP ..............................................................195, 205, 246 Software Simulator (MPLAB SIM) .................................... 254 Special Features of the CPU ........................................... 195 Configuration Registers ....................................196-201 Special Function Registers ................................................ 39 Map ............................................................................ 42 SPI Mode Associated Registers ............................................... 133 Bus Mode Compatibility ........................................... 133 Effects of a RESET .................................................. 133 Master Mode ............................................................ 130 Master/Slave Connection ......................................... 129 Overview .................................................................. 125 Serial Clock .............................................................. 125 Serial Data In ........................................................... 125 Serial Data Out ........................................................ 125 Slave Mode .............................................................. 131 Slave Select ............................................................. 125 Slave Select Synchronization .................................. 131 Slave Synch Timing ................................................. 131 SLEEP Operation .................................................... 133 SPI Clock ................................................................. 130 SS .................................................................................... 125 SSPOV Status Flag ......................................................... 155
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PIC18FXX39
SSPSTAT Register R/W Bit ............................................................. 138, 139 Status Bits Significance and the Initialization Condition for RCON Register ............................................. 25 SUBFWB .......................................................................... 246 SUBLW ............................................................................ 247 SUBWF ............................................................................ 247 SUBWFB .......................................................................... 248 SWAPF ............................................................................ 248 CLKO and I/O .......................................................... 271 Clock Synchronization ............................................. 145 Clock/Instruction Cycle .............................................. 36 Example SPI Master Mode (CKE = 0) ..................... 276 Example SPI Master Mode (CKE = 1) ..................... 277 Example SPI Slave Mode (CKE = 0) ....................... 278 Example SPI Slave Mode (CKE = 1) ....................... 279 External Clock (All Modes except PLL) ................... 270 First START Bit Timing ............................................ 153 I2C Bus Data ............................................................ 280 I2C Bus START/STOP Bits ...................................... 280 I2C Master Mode (7 or 10-bit Transmission) ............ 156 I2C Master Mode (7-bit Reception) .......................... 157 I2C Slave Mode (10-bit Transmission) ..................... 143 I2C Slave Mode (7-bit Transmission) ....................... 141 I2C Slave Mode with SEN = 0 (10-bit Reception) ............................................ 142 I2C Slave Mode with SEN = 0 (7-bit Reception) .............................................. 140 I2C Slave Mode with SEN = 1 (10-bit Reception) ............................................ 147 I2C Slave Mode with SEN = 1 (7-bit Reception) .............................................. 146 Low Voltage Detect ................................................. 192 Master SSP I2C Bus Data ........................................ 282 Master SSP I2C Bus START/STOP Bits .................. 282 Parallel Slave Port (PIC18F4X39) ........................... 275 Parallel Slave Port (Read) ......................................... 97 Parallel Slave Port (Write) ......................................... 96 PWM (PWM1 and PWM2) ....................................... 274 PWM Output ............................................................ 123 Repeat START Condition ........................................ 154 RESET, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ................................. 272 Slave Mode General Call Address Sequence (7 or 10-bit Address Mode) .............................. 148 Slave Synchronization ............................................. 131 Slow Rise Time (MCLR Tied to VDD) ......................... 31 SPI Mode (Master Mode) ......................................... 130 SPI Mode (Slave Mode with CKE = 0) ..................... 132 SPI Mode (Slave Mode with CKE = 1) ..................... 132 Stop Condition Receive or Transmit Mode .............. 158 Synchronous Reception (Master Mode, SREN) ...... 178 Synchronous Transmission ..................................... 177 Synchronous Transmission (Through TXEN) .......... 177 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) .......................................... 31 Time-out Sequence on Power-up (MCLR Not Tied to VDD) Case 1 ............................................................... 30 Case 2 ............................................................... 30 Time-out Sequence on Power-up (MCLR Tied to VDD) .......................................... 30 Timer0 and Timer1 External Clock .......................... 273 USART Synchronous Receive (Master/Slave) ........ 284 USART Synchronous Transmission (Master/Slave) ................................................. 284 Wake-up from SLEEP via Interrupt .......................... 206 Timing Diagrams Requirements Master SSP I2C Bus START/STOP Bits .................. 282
T
TABLAT Register ............................................................... 54 Table Pointer Operations (table) ........................................ 54 TBLPTR Register ............................................................... 54 TBLRD ............................................................................. 249 TBLWT ............................................................................. 250 Time-out Sequence ............................................................ 24 Time-out in Various Sitations ..................................... 25 Timer0 ................................................................................ 99 16-bit Mode Timer Reads and Writes ...................... 101 Associated Registers ............................................... 101 Clock Source Edge Select (T0SE Bit) ...................... 101 Clock Source Select (T0CS Bit) ............................... 101 Operation ................................................................. 101 Overflow Interrupt .................................................... 101 Prescaler. See Prescaler, Timer0 Timer1 .............................................................................. 103 16-bit Read/Write Mode ........................................... 105 Associated Registers ............................................... 105 Operation ................................................................. 104 Oscillator .................................................................. 103 Overflow Interrupt ............................................ 103, 105 TMR1H Register ...................................................... 103 TMR1L Register ....................................................... 103 Timer2 .............................................................................. 107 TMR2 to PR2 Match Interrupt .................................. 123 Timer3 .............................................................................. 109 Associated Registers ............................................... 111 Operation ................................................................. 110 Oscillator .................................................................. 109 Overflow Interrupt ............................................ 109, 111 TMR3H Register ...................................................... 109 TMR3L Register ....................................................... 109 Timing Diagrams A/D Conversion ........................................................ 285 Acknowledge Sequence .......................................... 158 Asynchronous Reception ......................................... 175 Asynchronous Transmission .................................... 173 Asynchronous Transmission (Back to Back) ........... 173 Baud Rate Generator with Clock Arbitration ............ 152 BRG Reset Due to SDA Arbitration During START Condition ................................. 161 Brown-out Reset (BOR) ........................................... 272 Bus Collision During a STOP Condition (Case 1) ........................................................... 163 Bus Collision During a STOP Condition (Case 2) ........................................................... 163 Bus Collision During Repeated START Condition (Case 1) ........................................... 162 Bus Collision During Repeated START Condition (Case 2) ........................................... 162 Bus Collision During START Condition (SCL = 0) ......................................................... 161 Bus Collision During Start Condition (SDA Only) ....................................................... 160 Bus Collision for Transmit and Acknowledge ........... 159 2002 Microchip Technology Inc.
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PIC18FXX39
Timing Requirements A/D Conversion ........................................................ 286 CLKO and I/O ........................................................... 271 Example SPI Mode (Master Mode, CKE = 0) .......... 276 Example SPI Mode (Master Mode, CKE = 1) .......... 277 Example SPI Mode (Slave Mode, CKE = 0) ............ 278 Example SPI Slave Mode (CKE = 1) ....................... 279 External Clock .......................................................... 270 I2C Bus Data (Slave Mode) ...................................... 281 Master SSP I2C Bus Data ........................................ 283 Parallel Slave Port (PIC18F4X39) ............................ 275 PWM ........................................................................ 274 RESET, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ....................... 272 Timer0 and Timer1 External Clock ........................... 273 USART Synchronous Receive ................................. 284 USART Synchronous Transmission ......................... 284 Timing Specifications PLL Clock ................................................................. 270 TRISE Register PSPMODE Bit ...................................................... 91, 96 TSTFSZ ............................................................................ 251 Two-Word Instructions Example Cases .......................................................... 38 TXSTA Register BRGH Bit .................................................................. 168
W
Wake-up from SLEEP ...............................................195, 205 Using Interrupts ....................................................... 205 Watchdog Timer (WDT) ............................................195, 203 Associated Registers ............................................... 204 Control Register ....................................................... 203 Postscaler .........................................................203, 204 Programming Considerations .................................. 203 RC Oscillator ............................................................ 203 Time-out Period ....................................................... 203 WCOL .............................................................................. 153 WCOL Status Flag ............................................153, 155, 158 WWW, On-Line Support ...................................................... 5
X
XORLW ............................................................................ 251 XORWF ........................................................................... 252
U
USART ............................................................................. 165 Asynchronous Mode ................................................ 172 Associated Registers, Receive ........................ 175 Associated Registers, Transmit ....................... 173 Receiver ........................................................... 174 Transmitter ....................................................... 172 Baud Rate Generator (BRG) .................................... 168 Associated Registers ....................................... 168 Baud Rate Error, Calculating ........................... 168 Baud Rate Formula .......................................... 168 Baud Rates for Asynchronous Mode (BRGH = 0) .............................................. 170 Baud Rates for Asynchronous Mode (BRGH = 1) .............................................. 171 Baud Rates for Synchronous Mode ................. 169 High Baud Rate Select (BRGH Bit) .................. 168 Sampling .......................................................... 168 Serial Port Enable (SPEN Bit) .................................. 165 Synchronous Master Mode ...................................... 176 Associated Registers, Reception ..................... 178 Associated Registers, Transmit ....................... 176 Reception ......................................................... 178 Transmission .................................................... 176 Synchronous Slave Mode ........................................ 179 Associated Registers, Receive ........................ 180 Associated Registers, Transmit ....................... 179 Reception ......................................................... 180 Transmission .................................................... 179
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2002 Microchip Technology Inc.
PIC18FXX39
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site.
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 092002
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
2002 Microchip Technology Inc.
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DS30485A-page 317
PIC18FXX39
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18FXX39 Questions: 1. What are the best features of this document? Y N Literature Number: DS30485A FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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2002 Microchip Technology Inc.
PIC18FXX39
PIC18FXX39 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. Device
-
X Temperature Range
/XX Package
XXX Pattern
Examples: a) PIC18LF4539 - I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2439 - I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC18F4439 - E/P = Extended temp., PDIP package, normal VDD limits.
Device
PIC18FXX39(1), PIC18FXX39T(2); VDD range 4.2V to 5.5V PIC18LFXX39(1), PIC18LFXX39T(2); VDD range 2.0V to 5.5V I E ML P PT SO SP = = = = = = = -40C to +85C (Industrial) -40C to +125C (Extended) QFN (Quad Flatpack, No Leads) PDIP TQFP (Plastic Thin Quad Flatpack) SOIC Skinny Plastic DIP
b) c)
Temperature Range Package
Note 1: F LF 2: T
= Standard Voltage range = Wide Voltage Range = in tape and reel - SOIC, QFN, and TQFP packages only.
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
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WORLDWIDE SALES AND SERVICE
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Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
China - Hong Kong SAR
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
France
Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-82966626
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
Germany
Microchip Technology GmbH Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
China - Qingdao
Rm. B503, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Italy
Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
12/05/02
DS30485A-page 320
Preliminary
2002 Microchip Technology Inc.

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